mpc8379_mds.dts 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MPC8379E MDS Device Tree Source
  4. *
  5. * Copyright 2007 Freescale Semiconductor Inc.
  6. */
  7. /dts-v1/;
  8. / {
  9. model = "fsl,mpc8379emds";
  10. compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. aliases {
  14. ethernet0 = &enet0;
  15. ethernet1 = &enet1;
  16. serial0 = &serial0;
  17. serial1 = &serial1;
  18. pci0 = &pci0;
  19. };
  20. cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. PowerPC,8379@0 {
  24. device_type = "cpu";
  25. reg = <0x0>;
  26. d-cache-line-size = <32>;
  27. i-cache-line-size = <32>;
  28. d-cache-size = <32768>;
  29. i-cache-size = <32768>;
  30. timebase-frequency = <0>;
  31. bus-frequency = <0>;
  32. clock-frequency = <0>;
  33. };
  34. };
  35. memory {
  36. device_type = "memory";
  37. reg = <0x00000000 0x20000000>; // 512MB at 0
  38. };
  39. localbus@e0005000 {
  40. #address-cells = <2>;
  41. #size-cells = <1>;
  42. compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
  43. reg = <0xe0005000 0x1000>;
  44. interrupts = <77 0x8>;
  45. interrupt-parent = <&ipic>;
  46. // booting from NOR flash
  47. ranges = <0 0x0 0xfe000000 0x02000000
  48. 1 0x0 0xf8000000 0x00008000
  49. 3 0x0 0xe0600000 0x00008000>;
  50. flash@0,0 {
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. compatible = "cfi-flash";
  54. reg = <0 0x0 0x2000000>;
  55. bank-width = <2>;
  56. device-width = <1>;
  57. u-boot@0 {
  58. reg = <0x0 0x100000>;
  59. read-only;
  60. };
  61. fs@100000 {
  62. reg = <0x100000 0x800000>;
  63. };
  64. kernel@1d00000 {
  65. reg = <0x1d00000 0x200000>;
  66. };
  67. dtb@1f00000 {
  68. reg = <0x1f00000 0x100000>;
  69. };
  70. };
  71. bcsr@1,0 {
  72. reg = <1 0x0 0x8000>;
  73. compatible = "fsl,mpc837xmds-bcsr";
  74. };
  75. nand@3,0 {
  76. #address-cells = <1>;
  77. #size-cells = <1>;
  78. compatible = "fsl,mpc8379-fcm-nand",
  79. "fsl,elbc-fcm-nand";
  80. reg = <3 0x0 0x8000>;
  81. u-boot@0 {
  82. reg = <0x0 0x100000>;
  83. read-only;
  84. };
  85. kernel@100000 {
  86. reg = <0x100000 0x300000>;
  87. };
  88. fs@400000 {
  89. reg = <0x400000 0x1c00000>;
  90. };
  91. };
  92. };
  93. soc@e0000000 {
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. device_type = "soc";
  97. compatible = "simple-bus";
  98. ranges = <0x0 0xe0000000 0x00100000>;
  99. reg = <0xe0000000 0x00000200>;
  100. bus-frequency = <0>;
  101. wdt@200 {
  102. compatible = "mpc83xx_wdt";
  103. reg = <0x200 0x100>;
  104. };
  105. sleep-nexus {
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. compatible = "simple-bus";
  109. sleep = <&pmc 0x0c000000>;
  110. ranges;
  111. i2c@3000 {
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. cell-index = <0>;
  115. compatible = "fsl-i2c";
  116. reg = <0x3000 0x100>;
  117. interrupts = <14 0x8>;
  118. interrupt-parent = <&ipic>;
  119. dfsrr;
  120. rtc@68 {
  121. compatible = "dallas,ds1374";
  122. reg = <0x68>;
  123. interrupts = <19 0x8>;
  124. interrupt-parent = <&ipic>;
  125. };
  126. };
  127. sdhci@2e000 {
  128. compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
  129. reg = <0x2e000 0x1000>;
  130. interrupts = <42 0x8>;
  131. interrupt-parent = <&ipic>;
  132. sdhci,wp-inverted;
  133. /* Filled in by U-Boot */
  134. clock-frequency = <0>;
  135. };
  136. };
  137. i2c@3100 {
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. cell-index = <1>;
  141. compatible = "fsl-i2c";
  142. reg = <0x3100 0x100>;
  143. interrupts = <15 0x8>;
  144. interrupt-parent = <&ipic>;
  145. dfsrr;
  146. };
  147. spi@7000 {
  148. cell-index = <0>;
  149. compatible = "fsl,spi";
  150. reg = <0x7000 0x1000>;
  151. interrupts = <16 0x8>;
  152. interrupt-parent = <&ipic>;
  153. mode = "cpu";
  154. };
  155. dma@82a8 {
  156. #address-cells = <1>;
  157. #size-cells = <1>;
  158. compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
  159. reg = <0x82a8 4>;
  160. ranges = <0 0x8100 0x1a8>;
  161. interrupt-parent = <&ipic>;
  162. interrupts = <71 8>;
  163. cell-index = <0>;
  164. dma-channel@0 {
  165. compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
  166. reg = <0 0x80>;
  167. cell-index = <0>;
  168. interrupt-parent = <&ipic>;
  169. interrupts = <71 8>;
  170. };
  171. dma-channel@80 {
  172. compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
  173. reg = <0x80 0x80>;
  174. cell-index = <1>;
  175. interrupt-parent = <&ipic>;
  176. interrupts = <71 8>;
  177. };
  178. dma-channel@100 {
  179. compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
  180. reg = <0x100 0x80>;
  181. cell-index = <2>;
  182. interrupt-parent = <&ipic>;
  183. interrupts = <71 8>;
  184. };
  185. dma-channel@180 {
  186. compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
  187. reg = <0x180 0x28>;
  188. cell-index = <3>;
  189. interrupt-parent = <&ipic>;
  190. interrupts = <71 8>;
  191. };
  192. };
  193. usb@23000 {
  194. compatible = "fsl-usb2-dr";
  195. reg = <0x23000 0x1000>;
  196. #address-cells = <1>;
  197. #size-cells = <0>;
  198. interrupt-parent = <&ipic>;
  199. interrupts = <38 0x8>;
  200. dr_mode = "host";
  201. phy_type = "ulpi";
  202. sleep = <&pmc 0x00c00000>;
  203. };
  204. enet0: ethernet@24000 {
  205. #address-cells = <1>;
  206. #size-cells = <1>;
  207. cell-index = <0>;
  208. device_type = "network";
  209. model = "eTSEC";
  210. compatible = "gianfar";
  211. reg = <0x24000 0x1000>;
  212. ranges = <0x0 0x24000 0x1000>;
  213. local-mac-address = [ 00 00 00 00 00 00 ];
  214. interrupts = <32 0x8 33 0x8 34 0x8>;
  215. phy-connection-type = "mii";
  216. interrupt-parent = <&ipic>;
  217. tbi-handle = <&tbi0>;
  218. phy-handle = <&phy2>;
  219. sleep = <&pmc 0xc0000000>;
  220. fsl,magic-packet;
  221. mdio@520 {
  222. #address-cells = <1>;
  223. #size-cells = <0>;
  224. compatible = "fsl,gianfar-mdio";
  225. reg = <0x520 0x20>;
  226. phy2: ethernet-phy@2 {
  227. interrupt-parent = <&ipic>;
  228. interrupts = <17 0x8>;
  229. reg = <0x2>;
  230. };
  231. phy3: ethernet-phy@3 {
  232. interrupt-parent = <&ipic>;
  233. interrupts = <18 0x8>;
  234. reg = <0x3>;
  235. };
  236. tbi0: tbi-phy@11 {
  237. reg = <0x11>;
  238. device_type = "tbi-phy";
  239. };
  240. };
  241. };
  242. enet1: ethernet@25000 {
  243. #address-cells = <1>;
  244. #size-cells = <1>;
  245. cell-index = <1>;
  246. device_type = "network";
  247. model = "eTSEC";
  248. compatible = "gianfar";
  249. reg = <0x25000 0x1000>;
  250. ranges = <0x0 0x25000 0x1000>;
  251. local-mac-address = [ 00 00 00 00 00 00 ];
  252. interrupts = <35 0x8 36 0x8 37 0x8>;
  253. phy-connection-type = "mii";
  254. interrupt-parent = <&ipic>;
  255. tbi-handle = <&tbi1>;
  256. phy-handle = <&phy3>;
  257. sleep = <&pmc 0x30000000>;
  258. fsl,magic-packet;
  259. mdio@520 {
  260. #address-cells = <1>;
  261. #size-cells = <0>;
  262. compatible = "fsl,gianfar-tbi";
  263. reg = <0x520 0x20>;
  264. tbi1: tbi-phy@11 {
  265. reg = <0x11>;
  266. device_type = "tbi-phy";
  267. };
  268. };
  269. };
  270. serial0: serial@4500 {
  271. cell-index = <0>;
  272. device_type = "serial";
  273. compatible = "fsl,ns16550", "ns16550";
  274. reg = <0x4500 0x100>;
  275. clock-frequency = <0>;
  276. interrupts = <9 0x8>;
  277. interrupt-parent = <&ipic>;
  278. };
  279. serial1: serial@4600 {
  280. cell-index = <1>;
  281. device_type = "serial";
  282. compatible = "fsl,ns16550", "ns16550";
  283. reg = <0x4600 0x100>;
  284. clock-frequency = <0>;
  285. interrupts = <10 0x8>;
  286. interrupt-parent = <&ipic>;
  287. };
  288. crypto@30000 {
  289. compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
  290. "fsl,sec2.1", "fsl,sec2.0";
  291. reg = <0x30000 0x10000>;
  292. interrupts = <11 0x8>;
  293. interrupt-parent = <&ipic>;
  294. fsl,num-channels = <4>;
  295. fsl,channel-fifo-len = <24>;
  296. fsl,exec-units-mask = <0x9fe>;
  297. fsl,descriptor-types-mask = <0x3ab0ebf>;
  298. sleep = <&pmc 0x03000000>;
  299. };
  300. sata@18000 {
  301. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  302. reg = <0x18000 0x1000>;
  303. interrupts = <44 0x8>;
  304. interrupt-parent = <&ipic>;
  305. sleep = <&pmc 0x000000c0>;
  306. };
  307. sata@19000 {
  308. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  309. reg = <0x19000 0x1000>;
  310. interrupts = <45 0x8>;
  311. interrupt-parent = <&ipic>;
  312. sleep = <&pmc 0x00000030>;
  313. };
  314. sata@1a000 {
  315. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  316. reg = <0x1a000 0x1000>;
  317. interrupts = <46 0x8>;
  318. interrupt-parent = <&ipic>;
  319. sleep = <&pmc 0x0000000c>;
  320. };
  321. sata@1b000 {
  322. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  323. reg = <0x1b000 0x1000>;
  324. interrupts = <47 0x8>;
  325. interrupt-parent = <&ipic>;
  326. sleep = <&pmc 0x00000003>;
  327. };
  328. /* IPIC
  329. * interrupts cell = <intr #, sense>
  330. * sense values match linux IORESOURCE_IRQ_* defines:
  331. * sense == 8: Level, low assertion
  332. * sense == 2: Edge, high-to-low change
  333. */
  334. ipic: pic@700 {
  335. compatible = "fsl,ipic";
  336. interrupt-controller;
  337. #address-cells = <0>;
  338. #interrupt-cells = <2>;
  339. reg = <0x700 0x100>;
  340. };
  341. pmc: power@b00 {
  342. compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
  343. reg = <0xb00 0x100 0xa00 0x100>;
  344. interrupts = <80 0x8>;
  345. interrupt-parent = <&ipic>;
  346. };
  347. };
  348. pci0: pci@e0008500 {
  349. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  350. interrupt-map = <
  351. /* IDSEL 0x11 */
  352. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  353. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  354. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  355. 0x8800 0x0 0x0 0x4 &ipic 23 0x8
  356. /* IDSEL 0x12 */
  357. 0x9000 0x0 0x0 0x1 &ipic 22 0x8
  358. 0x9000 0x0 0x0 0x2 &ipic 23 0x8
  359. 0x9000 0x0 0x0 0x3 &ipic 20 0x8
  360. 0x9000 0x0 0x0 0x4 &ipic 21 0x8
  361. /* IDSEL 0x13 */
  362. 0x9800 0x0 0x0 0x1 &ipic 23 0x8
  363. 0x9800 0x0 0x0 0x2 &ipic 20 0x8
  364. 0x9800 0x0 0x0 0x3 &ipic 21 0x8
  365. 0x9800 0x0 0x0 0x4 &ipic 22 0x8
  366. /* IDSEL 0x15 */
  367. 0xa800 0x0 0x0 0x1 &ipic 20 0x8
  368. 0xa800 0x0 0x0 0x2 &ipic 21 0x8
  369. 0xa800 0x0 0x0 0x3 &ipic 22 0x8
  370. 0xa800 0x0 0x0 0x4 &ipic 23 0x8
  371. /* IDSEL 0x16 */
  372. 0xb000 0x0 0x0 0x1 &ipic 23 0x8
  373. 0xb000 0x0 0x0 0x2 &ipic 20 0x8
  374. 0xb000 0x0 0x0 0x3 &ipic 21 0x8
  375. 0xb000 0x0 0x0 0x4 &ipic 22 0x8
  376. /* IDSEL 0x17 */
  377. 0xb800 0x0 0x0 0x1 &ipic 22 0x8
  378. 0xb800 0x0 0x0 0x2 &ipic 23 0x8
  379. 0xb800 0x0 0x0 0x3 &ipic 20 0x8
  380. 0xb800 0x0 0x0 0x4 &ipic 21 0x8
  381. /* IDSEL 0x18 */
  382. 0xc000 0x0 0x0 0x1 &ipic 21 0x8
  383. 0xc000 0x0 0x0 0x2 &ipic 22 0x8
  384. 0xc000 0x0 0x0 0x3 &ipic 23 0x8
  385. 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
  386. interrupt-parent = <&ipic>;
  387. interrupts = <66 0x8>;
  388. bus-range = <0x0 0x0>;
  389. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  390. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  391. 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
  392. sleep = <&pmc 0x00010000>;
  393. clock-frequency = <0>;
  394. #interrupt-cells = <1>;
  395. #size-cells = <2>;
  396. #address-cells = <3>;
  397. reg = <0xe0008500 0x100 /* internal registers */
  398. 0xe0008300 0x8>; /* config space access registers */
  399. compatible = "fsl,mpc8349-pci";
  400. device_type = "pci";
  401. };
  402. };