mpc8349emitx.dts 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MPC8349E-mITX Device Tree Source
  4. *
  5. * Copyright 2006 Freescale Semiconductor Inc.
  6. */
  7. /dts-v1/;
  8. / {
  9. model = "MPC8349EMITX";
  10. compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. aliases {
  14. ethernet0 = &enet0;
  15. ethernet1 = &enet1;
  16. serial0 = &serial0;
  17. serial1 = &serial1;
  18. pci0 = &pci0;
  19. pci1 = &pci1;
  20. };
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. PowerPC,8349@0 {
  25. device_type = "cpu";
  26. reg = <0x0>;
  27. d-cache-line-size = <32>;
  28. i-cache-line-size = <32>;
  29. d-cache-size = <32768>;
  30. i-cache-size = <32768>;
  31. timebase-frequency = <0>; // from bootloader
  32. bus-frequency = <0>; // from bootloader
  33. clock-frequency = <0>; // from bootloader
  34. };
  35. };
  36. memory {
  37. device_type = "memory";
  38. reg = <0x00000000 0x10000000>;
  39. };
  40. soc8349@e0000000 {
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. device_type = "soc";
  44. compatible = "simple-bus";
  45. ranges = <0x0 0xe0000000 0x00100000>;
  46. reg = <0xe0000000 0x00000200>;
  47. bus-frequency = <0>; // from bootloader
  48. wdt@200 {
  49. device_type = "watchdog";
  50. compatible = "mpc83xx_wdt";
  51. reg = <0x200 0x100>;
  52. };
  53. gpio1: gpio-controller@c00 {
  54. #gpio-cells = <2>;
  55. compatible = "fsl,mpc8349-gpio";
  56. reg = <0xc00 0x100>;
  57. interrupts = <74 0x8>;
  58. interrupt-parent = <&ipic>;
  59. gpio-controller;
  60. };
  61. gpio2: gpio-controller@d00 {
  62. #gpio-cells = <2>;
  63. compatible = "fsl,mpc8349-gpio";
  64. reg = <0xd00 0x100>;
  65. interrupts = <75 0x8>;
  66. interrupt-parent = <&ipic>;
  67. gpio-controller;
  68. };
  69. i2c@3000 {
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. cell-index = <0>;
  73. compatible = "fsl-i2c";
  74. reg = <0x3000 0x100>;
  75. interrupts = <14 0x8>;
  76. interrupt-parent = <&ipic>;
  77. dfsrr;
  78. eeprom: at24@50 {
  79. compatible = "st,24c256", "atmel,24c256";
  80. reg = <0x50>;
  81. };
  82. };
  83. i2c@3100 {
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. cell-index = <1>;
  87. compatible = "fsl-i2c";
  88. reg = <0x3100 0x100>;
  89. interrupts = <15 0x8>;
  90. interrupt-parent = <&ipic>;
  91. dfsrr;
  92. rtc@68 {
  93. compatible = "dallas,ds1339";
  94. reg = <0x68>;
  95. interrupts = <18 0x8>;
  96. interrupt-parent = <&ipic>;
  97. };
  98. pcf1: iexp@38 {
  99. #gpio-cells = <2>;
  100. compatible = "ti,pcf8574a";
  101. reg = <0x38>;
  102. gpio-controller;
  103. };
  104. pcf2: iexp@39 {
  105. #gpio-cells = <2>;
  106. compatible = "ti,pcf8574a";
  107. reg = <0x39>;
  108. gpio-controller;
  109. };
  110. spd: at24@51 {
  111. compatible = "atmel,spd";
  112. reg = <0x51>;
  113. };
  114. mcu_pio: mcu@a {
  115. #gpio-cells = <2>;
  116. compatible = "fsl,mc9s08qg8-mpc8349emitx",
  117. "fsl,mcu-mpc8349emitx";
  118. reg = <0x0a>;
  119. gpio-controller;
  120. };
  121. };
  122. spi@7000 {
  123. cell-index = <0>;
  124. compatible = "fsl,spi";
  125. reg = <0x7000 0x1000>;
  126. interrupts = <16 0x8>;
  127. interrupt-parent = <&ipic>;
  128. mode = "cpu";
  129. };
  130. dma@82a8 {
  131. #address-cells = <1>;
  132. #size-cells = <1>;
  133. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  134. reg = <0x82a8 4>;
  135. ranges = <0 0x8100 0x1a8>;
  136. interrupt-parent = <&ipic>;
  137. interrupts = <71 8>;
  138. cell-index = <0>;
  139. dma-channel@0 {
  140. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  141. reg = <0 0x80>;
  142. cell-index = <0>;
  143. interrupt-parent = <&ipic>;
  144. interrupts = <71 8>;
  145. };
  146. dma-channel@80 {
  147. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  148. reg = <0x80 0x80>;
  149. cell-index = <1>;
  150. interrupt-parent = <&ipic>;
  151. interrupts = <71 8>;
  152. };
  153. dma-channel@100 {
  154. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  155. reg = <0x100 0x80>;
  156. cell-index = <2>;
  157. interrupt-parent = <&ipic>;
  158. interrupts = <71 8>;
  159. };
  160. dma-channel@180 {
  161. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  162. reg = <0x180 0x28>;
  163. cell-index = <3>;
  164. interrupt-parent = <&ipic>;
  165. interrupts = <71 8>;
  166. };
  167. };
  168. usb@22000 {
  169. compatible = "fsl-usb2-mph";
  170. reg = <0x22000 0x1000>;
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. interrupt-parent = <&ipic>;
  174. interrupts = <39 0x8>;
  175. phy_type = "ulpi";
  176. port0;
  177. };
  178. usb@23000 {
  179. compatible = "fsl-usb2-dr";
  180. reg = <0x23000 0x1000>;
  181. #address-cells = <1>;
  182. #size-cells = <0>;
  183. interrupt-parent = <&ipic>;
  184. interrupts = <38 0x8>;
  185. dr_mode = "peripheral";
  186. phy_type = "ulpi";
  187. };
  188. enet0: ethernet@24000 {
  189. #address-cells = <1>;
  190. #size-cells = <1>;
  191. cell-index = <0>;
  192. device_type = "network";
  193. model = "TSEC";
  194. compatible = "gianfar";
  195. reg = <0x24000 0x1000>;
  196. ranges = <0x0 0x24000 0x1000>;
  197. local-mac-address = [ 00 00 00 00 00 00 ];
  198. interrupts = <32 0x8 33 0x8 34 0x8>;
  199. interrupt-parent = <&ipic>;
  200. tbi-handle = <&tbi0>;
  201. phy-handle = <&phy1c>;
  202. linux,network-index = <0>;
  203. mdio@520 {
  204. #address-cells = <1>;
  205. #size-cells = <0>;
  206. compatible = "fsl,gianfar-mdio";
  207. reg = <0x520 0x20>;
  208. /* Vitesse 8201 */
  209. phy1c: ethernet-phy@1c {
  210. interrupt-parent = <&ipic>;
  211. interrupts = <18 0x8>;
  212. reg = <0x1c>;
  213. };
  214. tbi0: tbi-phy@11 {
  215. reg = <0x11>;
  216. device_type = "tbi-phy";
  217. };
  218. };
  219. };
  220. enet1: ethernet@25000 {
  221. #address-cells = <1>;
  222. #size-cells = <1>;
  223. cell-index = <1>;
  224. device_type = "network";
  225. model = "TSEC";
  226. compatible = "gianfar";
  227. reg = <0x25000 0x1000>;
  228. ranges = <0x0 0x25000 0x1000>;
  229. local-mac-address = [ 00 00 00 00 00 00 ];
  230. interrupts = <35 0x8 36 0x8 37 0x8>;
  231. interrupt-parent = <&ipic>;
  232. /* Vitesse 7385 isn't on the MDIO bus */
  233. fixed-link = <1 1 1000 0 0>;
  234. linux,network-index = <1>;
  235. tbi-handle = <&tbi1>;
  236. mdio@520 {
  237. #address-cells = <1>;
  238. #size-cells = <0>;
  239. compatible = "fsl,gianfar-tbi";
  240. reg = <0x520 0x20>;
  241. tbi1: tbi-phy@11 {
  242. reg = <0x11>;
  243. device_type = "tbi-phy";
  244. };
  245. };
  246. };
  247. serial0: serial@4500 {
  248. cell-index = <0>;
  249. device_type = "serial";
  250. compatible = "fsl,ns16550", "ns16550";
  251. reg = <0x4500 0x100>;
  252. clock-frequency = <0>; // from bootloader
  253. interrupts = <9 0x8>;
  254. interrupt-parent = <&ipic>;
  255. };
  256. serial1: serial@4600 {
  257. cell-index = <1>;
  258. device_type = "serial";
  259. compatible = "fsl,ns16550", "ns16550";
  260. reg = <0x4600 0x100>;
  261. clock-frequency = <0>; // from bootloader
  262. interrupts = <10 0x8>;
  263. interrupt-parent = <&ipic>;
  264. };
  265. crypto@30000 {
  266. compatible = "fsl,sec2.0";
  267. reg = <0x30000 0x10000>;
  268. interrupts = <11 0x8>;
  269. interrupt-parent = <&ipic>;
  270. fsl,num-channels = <4>;
  271. fsl,channel-fifo-len = <24>;
  272. fsl,exec-units-mask = <0x7e>;
  273. fsl,descriptor-types-mask = <0x01010ebf>;
  274. };
  275. ipic: pic@700 {
  276. interrupt-controller;
  277. #address-cells = <0>;
  278. #interrupt-cells = <2>;
  279. reg = <0x700 0x100>;
  280. device_type = "ipic";
  281. };
  282. gpio-leds {
  283. compatible = "gpio-leds";
  284. green {
  285. label = "Green";
  286. gpios = <&pcf1 0 1>;
  287. linux,default-trigger = "heartbeat";
  288. };
  289. yellow {
  290. label = "Yellow";
  291. gpios = <&pcf1 1 1>;
  292. /* linux,default-trigger = "heartbeat"; */
  293. default-state = "on";
  294. };
  295. };
  296. };
  297. pci0: pci@e0008500 {
  298. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  299. interrupt-map = <
  300. /* IDSEL 0x10 - SATA */
  301. 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
  302. >;
  303. interrupt-parent = <&ipic>;
  304. interrupts = <66 0x8>;
  305. bus-range = <0x0 0x0>;
  306. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  307. 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  308. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
  309. clock-frequency = <66666666>;
  310. #interrupt-cells = <1>;
  311. #size-cells = <2>;
  312. #address-cells = <3>;
  313. reg = <0xe0008500 0x100 /* internal registers */
  314. 0xe0008300 0x8>; /* config space access registers */
  315. compatible = "fsl,mpc8349-pci";
  316. device_type = "pci";
  317. };
  318. pci1: pci@e0008600 {
  319. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  320. interrupt-map = <
  321. /* IDSEL 0x0E - MiniPCI Slot */
  322. 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
  323. /* IDSEL 0x0F - PCI Slot */
  324. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  325. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  326. >;
  327. interrupt-parent = <&ipic>;
  328. interrupts = <67 0x8>;
  329. bus-range = <0x0 0x0>;
  330. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  331. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  332. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  333. clock-frequency = <66666666>;
  334. #interrupt-cells = <1>;
  335. #size-cells = <2>;
  336. #address-cells = <3>;
  337. reg = <0xe0008600 0x100 /* internal registers */
  338. 0xe0008380 0x8>; /* config space access registers */
  339. compatible = "fsl,mpc8349-pci";
  340. device_type = "pci";
  341. };
  342. localbus@e0005000 {
  343. #address-cells = <2>;
  344. #size-cells = <1>;
  345. compatible = "fsl,mpc8349e-localbus",
  346. "fsl,pq2pro-localbus",
  347. "simple-bus";
  348. reg = <0xe0005000 0xd8>;
  349. ranges = <0x0 0x0 0xfe000000 0x1000000 /* flash */
  350. 0x1 0x0 0xf8000000 0x20000 /* VSC 7385 */
  351. 0x2 0x0 0xf9000000 0x200000 /* exp slot */
  352. 0x3 0x0 0xf0000000 0x210>; /* CF slot */
  353. flash@0,0 {
  354. compatible = "cfi-flash";
  355. reg = <0x0 0x0 0x800000>;
  356. bank-width = <2>;
  357. device-width = <1>;
  358. };
  359. flash@0,800000 {
  360. #address-cells = <1>;
  361. #size-cells = <1>;
  362. compatible = "cfi-flash";
  363. reg = <0x0 0x800000 0x800000>;
  364. bank-width = <2>;
  365. device-width = <1>;
  366. };
  367. pata@3,0 {
  368. compatible = "fsl,mpc8349emitx-pata", "ata-generic";
  369. reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
  370. reg-shift = <1>;
  371. pio-mode = <6>;
  372. interrupts = <23 0x8>;
  373. interrupt-parent = <&ipic>;
  374. };
  375. };
  376. };