mpc8272ads.dts 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MPC8272 ADS Device Tree Source
  4. *
  5. * Copyright 2005,2008 Freescale Semiconductor Inc.
  6. */
  7. /dts-v1/;
  8. / {
  9. model = "MPC8272ADS";
  10. compatible = "fsl,mpc8272ads";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. aliases {
  14. ethernet0 = &eth0;
  15. ethernet1 = &eth1;
  16. serial0 = &scc1;
  17. serial1 = &scc4;
  18. };
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. PowerPC,8272@0 {
  23. device_type = "cpu";
  24. reg = <0x0>;
  25. d-cache-line-size = <32>;
  26. i-cache-line-size = <32>;
  27. d-cache-size = <16384>;
  28. i-cache-size = <16384>;
  29. timebase-frequency = <0>;
  30. bus-frequency = <0>;
  31. clock-frequency = <0>;
  32. };
  33. };
  34. memory {
  35. device_type = "memory";
  36. reg = <0x0 0x0>;
  37. };
  38. localbus@f0010100 {
  39. compatible = "fsl,mpc8272-localbus",
  40. "fsl,pq2-localbus";
  41. #address-cells = <2>;
  42. #size-cells = <1>;
  43. reg = <0xf0010100 0x40>;
  44. ranges = <0x0 0x0 0xff800000 0x00800000
  45. 0x1 0x0 0xf4500000 0x8000
  46. 0x3 0x0 0xf8200000 0x8000>;
  47. flash@0,0 {
  48. compatible = "jedec-flash";
  49. reg = <0x0 0x0 0x00800000>;
  50. bank-width = <4>;
  51. device-width = <1>;
  52. };
  53. board-control@1,0 {
  54. reg = <0x1 0x0 0x20>;
  55. compatible = "fsl,mpc8272ads-bcsr";
  56. };
  57. PCI_PIC: interrupt-controller@3,0 {
  58. compatible = "fsl,mpc8272ads-pci-pic",
  59. "fsl,pq2ads-pci-pic";
  60. #interrupt-cells = <1>;
  61. interrupt-controller;
  62. reg = <0x3 0x0 0x8>;
  63. interrupt-parent = <&PIC>;
  64. interrupts = <20 8>;
  65. };
  66. };
  67. pci@f0010800 {
  68. device_type = "pci";
  69. reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
  70. compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
  71. #interrupt-cells = <1>;
  72. #size-cells = <2>;
  73. #address-cells = <3>;
  74. clock-frequency = <66666666>;
  75. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  76. interrupt-map = <
  77. /* IDSEL 0x16 */
  78. 0xb000 0x0 0x0 0x1 &PCI_PIC 0
  79. 0xb000 0x0 0x0 0x2 &PCI_PIC 1
  80. 0xb000 0x0 0x0 0x3 &PCI_PIC 2
  81. 0xb000 0x0 0x0 0x4 &PCI_PIC 3
  82. /* IDSEL 0x17 */
  83. 0xb800 0x0 0x0 0x1 &PCI_PIC 4
  84. 0xb800 0x0 0x0 0x2 &PCI_PIC 5
  85. 0xb800 0x0 0x0 0x3 &PCI_PIC 6
  86. 0xb800 0x0 0x0 0x4 &PCI_PIC 7
  87. /* IDSEL 0x18 */
  88. 0xc000 0x0 0x0 0x1 &PCI_PIC 8
  89. 0xc000 0x0 0x0 0x2 &PCI_PIC 9
  90. 0xc000 0x0 0x0 0x3 &PCI_PIC 10
  91. 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
  92. interrupt-parent = <&PIC>;
  93. interrupts = <18 8>;
  94. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
  95. 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
  96. 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
  97. };
  98. soc@f0000000 {
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. device_type = "soc";
  102. compatible = "fsl,mpc8272", "fsl,pq2-soc";
  103. ranges = <0x0 0xf0000000 0x53000>;
  104. // Temporary -- will go away once kernel uses ranges for get_immrbase().
  105. reg = <0xf0000000 0x53000>;
  106. cpm@119c0 {
  107. #address-cells = <1>;
  108. #size-cells = <1>;
  109. compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
  110. reg = <0x119c0 0x30>;
  111. ranges;
  112. muram@0 {
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. ranges = <0x0 0x0 0x10000>;
  116. data@0 {
  117. compatible = "fsl,cpm-muram-data";
  118. reg = <0x0 0x2000 0x9800 0x800>;
  119. };
  120. };
  121. brg@119f0 {
  122. compatible = "fsl,mpc8272-brg",
  123. "fsl,cpm2-brg",
  124. "fsl,cpm-brg";
  125. reg = <0x119f0 0x10 0x115f0 0x10>;
  126. };
  127. scc1: serial@11a00 {
  128. device_type = "serial";
  129. compatible = "fsl,mpc8272-scc-uart",
  130. "fsl,cpm2-scc-uart";
  131. reg = <0x11a00 0x20 0x8000 0x100>;
  132. interrupts = <40 8>;
  133. interrupt-parent = <&PIC>;
  134. fsl,cpm-brg = <1>;
  135. fsl,cpm-command = <0x800000>;
  136. };
  137. scc4: serial@11a60 {
  138. device_type = "serial";
  139. compatible = "fsl,mpc8272-scc-uart",
  140. "fsl,cpm2-scc-uart";
  141. reg = <0x11a60 0x20 0x8300 0x100>;
  142. interrupts = <43 8>;
  143. interrupt-parent = <&PIC>;
  144. fsl,cpm-brg = <4>;
  145. fsl,cpm-command = <0xce00000>;
  146. };
  147. usb@11b60 {
  148. compatible = "fsl,mpc8272-cpm-usb";
  149. reg = <0x11b60 0x40 0x8b00 0x100>;
  150. interrupts = <11 8>;
  151. interrupt-parent = <&PIC>;
  152. mode = "peripheral";
  153. };
  154. mdio@10d40 {
  155. compatible = "fsl,mpc8272ads-mdio-bitbang",
  156. "fsl,mpc8272-mdio-bitbang",
  157. "fsl,cpm2-mdio-bitbang";
  158. reg = <0x10d40 0x14>;
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. fsl,mdio-pin = <18>;
  162. fsl,mdc-pin = <19>;
  163. PHY0: ethernet-phy@0 {
  164. interrupt-parent = <&PIC>;
  165. interrupts = <23 8>;
  166. reg = <0x0>;
  167. };
  168. PHY1: ethernet-phy@1 {
  169. interrupt-parent = <&PIC>;
  170. interrupts = <23 8>;
  171. reg = <0x3>;
  172. };
  173. };
  174. eth0: ethernet@11300 {
  175. device_type = "network";
  176. compatible = "fsl,mpc8272-fcc-enet",
  177. "fsl,cpm2-fcc-enet";
  178. reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
  179. local-mac-address = [ 00 00 00 00 00 00 ];
  180. interrupts = <32 8>;
  181. interrupt-parent = <&PIC>;
  182. phy-handle = <&PHY0>;
  183. linux,network-index = <0>;
  184. fsl,cpm-command = <0x12000300>;
  185. };
  186. eth1: ethernet@11320 {
  187. device_type = "network";
  188. compatible = "fsl,mpc8272-fcc-enet",
  189. "fsl,cpm2-fcc-enet";
  190. reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
  191. local-mac-address = [ 00 00 00 00 00 00 ];
  192. interrupts = <33 8>;
  193. interrupt-parent = <&PIC>;
  194. phy-handle = <&PHY1>;
  195. linux,network-index = <1>;
  196. fsl,cpm-command = <0x16200300>;
  197. };
  198. i2c@11860 {
  199. compatible = "fsl,mpc8272-i2c",
  200. "fsl,cpm2-i2c";
  201. reg = <0x11860 0x20 0x8afc 0x2>;
  202. interrupts = <1 8>;
  203. interrupt-parent = <&PIC>;
  204. fsl,cpm-command = <0x29600000>;
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. };
  208. };
  209. PIC: interrupt-controller@10c00 {
  210. #interrupt-cells = <2>;
  211. interrupt-controller;
  212. reg = <0x10c00 0x80>;
  213. compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
  214. };
  215. crypto@30000 {
  216. compatible = "fsl,sec1.0";
  217. reg = <0x40000 0x13000>;
  218. interrupts = <47 0x8>;
  219. interrupt-parent = <&PIC>;
  220. fsl,num-channels = <4>;
  221. fsl,channel-fifo-len = <24>;
  222. fsl,exec-units-mask = <0x7e>;
  223. fsl,descriptor-types-mask = <0x1010415>;
  224. };
  225. };
  226. chosen {
  227. stdout-path = "/soc/cpm/serial@11a00";
  228. };
  229. };