t4240si-post.dtsi 28 KB

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  1. /*
  2. * T4240 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &bman_fbpr {
  35. compatible = "fsl,bman-fbpr";
  36. alloc-ranges = <0 0 0x10000 0>;
  37. };
  38. &qman_fqd {
  39. compatible = "fsl,qman-fqd";
  40. alloc-ranges = <0 0 0x10000 0>;
  41. };
  42. &qman_pfdr {
  43. compatible = "fsl,qman-pfdr";
  44. alloc-ranges = <0 0 0x10000 0>;
  45. };
  46. &ifc {
  47. #address-cells = <2>;
  48. #size-cells = <1>;
  49. compatible = "fsl,ifc", "simple-bus";
  50. interrupts = <25 2 0 0>;
  51. };
  52. /* controller at 0x240000 */
  53. &pci0 {
  54. compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
  55. device_type = "pci";
  56. #size-cells = <2>;
  57. #address-cells = <3>;
  58. bus-range = <0x0 0xff>;
  59. interrupts = <20 2 0 0>;
  60. pcie@0 {
  61. #interrupt-cells = <1>;
  62. #size-cells = <2>;
  63. #address-cells = <3>;
  64. device_type = "pci";
  65. reg = <0 0 0 0 0>;
  66. interrupts = <20 2 0 0>;
  67. interrupt-map-mask = <0xf800 0 0 7>;
  68. interrupt-map = <
  69. /* IDSEL 0x0 */
  70. 0000 0 0 1 &mpic 40 1 0 0
  71. 0000 0 0 2 &mpic 1 1 0 0
  72. 0000 0 0 3 &mpic 2 1 0 0
  73. 0000 0 0 4 &mpic 3 1 0 0
  74. >;
  75. };
  76. };
  77. /* controller at 0x250000 */
  78. &pci1 {
  79. compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
  80. device_type = "pci";
  81. #size-cells = <2>;
  82. #address-cells = <3>;
  83. bus-range = <0 0xff>;
  84. interrupts = <21 2 0 0>;
  85. pcie@0 {
  86. #interrupt-cells = <1>;
  87. #size-cells = <2>;
  88. #address-cells = <3>;
  89. device_type = "pci";
  90. reg = <0 0 0 0 0>;
  91. interrupts = <21 2 0 0>;
  92. interrupt-map-mask = <0xf800 0 0 7>;
  93. interrupt-map = <
  94. /* IDSEL 0x0 */
  95. 0000 0 0 1 &mpic 41 1 0 0
  96. 0000 0 0 2 &mpic 5 1 0 0
  97. 0000 0 0 3 &mpic 6 1 0 0
  98. 0000 0 0 4 &mpic 7 1 0 0
  99. >;
  100. };
  101. };
  102. /* controller at 0x260000 */
  103. &pci2 {
  104. compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
  105. device_type = "pci";
  106. #size-cells = <2>;
  107. #address-cells = <3>;
  108. bus-range = <0x0 0xff>;
  109. interrupts = <22 2 0 0>;
  110. pcie@0 {
  111. #interrupt-cells = <1>;
  112. #size-cells = <2>;
  113. #address-cells = <3>;
  114. device_type = "pci";
  115. reg = <0 0 0 0 0>;
  116. interrupts = <22 2 0 0>;
  117. interrupt-map-mask = <0xf800 0 0 7>;
  118. interrupt-map = <
  119. /* IDSEL 0x0 */
  120. 0000 0 0 1 &mpic 42 1 0 0
  121. 0000 0 0 2 &mpic 9 1 0 0
  122. 0000 0 0 3 &mpic 10 1 0 0
  123. 0000 0 0 4 &mpic 11 1 0 0
  124. >;
  125. };
  126. };
  127. /* controller at 0x270000 */
  128. &pci3 {
  129. compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
  130. device_type = "pci";
  131. #size-cells = <2>;
  132. #address-cells = <3>;
  133. bus-range = <0x0 0xff>;
  134. interrupts = <23 2 0 0>;
  135. pcie@0 {
  136. #interrupt-cells = <1>;
  137. #size-cells = <2>;
  138. #address-cells = <3>;
  139. device_type = "pci";
  140. reg = <0 0 0 0 0>;
  141. interrupts = <23 2 0 0>;
  142. interrupt-map-mask = <0xf800 0 0 7>;
  143. interrupt-map = <
  144. /* IDSEL 0x0 */
  145. 0000 0 0 1 &mpic 43 1 0 0
  146. 0000 0 0 2 &mpic 0 1 0 0
  147. 0000 0 0 3 &mpic 4 1 0 0
  148. 0000 0 0 4 &mpic 8 1 0 0
  149. >;
  150. };
  151. };
  152. &rio {
  153. compatible = "fsl,srio";
  154. interrupts = <16 2 1 11>;
  155. #address-cells = <2>;
  156. #size-cells = <2>;
  157. ranges;
  158. port1 {
  159. #address-cells = <2>;
  160. #size-cells = <2>;
  161. cell-index = <1>;
  162. };
  163. port2 {
  164. #address-cells = <2>;
  165. #size-cells = <2>;
  166. cell-index = <2>;
  167. };
  168. };
  169. &dcsr {
  170. #address-cells = <1>;
  171. #size-cells = <1>;
  172. compatible = "fsl,dcsr", "simple-bus";
  173. dcsr-epu@0 {
  174. compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu";
  175. interrupts = <52 2 0 0
  176. 84 2 0 0
  177. 85 2 0 0
  178. 94 2 0 0
  179. 95 2 0 0>;
  180. reg = <0x0 0x1000>;
  181. };
  182. dcsr-npc {
  183. compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc";
  184. reg = <0x1000 0x1000 0x1002000 0x10000>;
  185. };
  186. dcsr-nxc@2000 {
  187. compatible = "fsl,dcsr-nxc";
  188. reg = <0x2000 0x1000>;
  189. };
  190. dcsr-corenet {
  191. compatible = "fsl,dcsr-corenet";
  192. reg = <0x8000 0x1000 0x1A000 0x1000>;
  193. };
  194. dcsr-dpaa@9000 {
  195. compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa";
  196. reg = <0x9000 0x1000>;
  197. };
  198. dcsr-ocn@11000 {
  199. compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn";
  200. reg = <0x11000 0x1000>;
  201. };
  202. dcsr-ddr@12000 {
  203. compatible = "fsl,dcsr-ddr";
  204. dev-handle = <&ddr1>;
  205. reg = <0x12000 0x1000>;
  206. };
  207. dcsr-ddr@13000 {
  208. compatible = "fsl,dcsr-ddr";
  209. dev-handle = <&ddr2>;
  210. reg = <0x13000 0x1000>;
  211. };
  212. dcsr-ddr@14000 {
  213. compatible = "fsl,dcsr-ddr";
  214. dev-handle = <&ddr3>;
  215. reg = <0x14000 0x1000>;
  216. };
  217. dcsr-nal@18000 {
  218. compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal";
  219. reg = <0x18000 0x1000>;
  220. };
  221. dcsr-rcpm@22000 {
  222. compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm";
  223. reg = <0x22000 0x1000>;
  224. };
  225. dcsr-snpc@30000 {
  226. compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
  227. reg = <0x30000 0x1000 0x1022000 0x10000>;
  228. };
  229. dcsr-snpc@31000 {
  230. compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
  231. reg = <0x31000 0x1000 0x1042000 0x10000>;
  232. };
  233. dcsr-snpc@32000 {
  234. compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
  235. reg = <0x32000 0x1000 0x1062000 0x10000>;
  236. };
  237. dcsr-cpu-sb-proxy@100000 {
  238. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  239. cpu-handle = <&cpu0>;
  240. reg = <0x100000 0x1000 0x101000 0x1000>;
  241. };
  242. dcsr-cpu-sb-proxy@108000 {
  243. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  244. cpu-handle = <&cpu1>;
  245. reg = <0x108000 0x1000 0x109000 0x1000>;
  246. };
  247. dcsr-cpu-sb-proxy@110000 {
  248. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  249. cpu-handle = <&cpu2>;
  250. reg = <0x110000 0x1000 0x111000 0x1000>;
  251. };
  252. dcsr-cpu-sb-proxy@118000 {
  253. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  254. cpu-handle = <&cpu3>;
  255. reg = <0x118000 0x1000 0x119000 0x1000>;
  256. };
  257. dcsr-cpu-sb-proxy@120000 {
  258. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  259. cpu-handle = <&cpu4>;
  260. reg = <0x120000 0x1000 0x121000 0x1000>;
  261. };
  262. dcsr-cpu-sb-proxy@128000 {
  263. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  264. cpu-handle = <&cpu5>;
  265. reg = <0x128000 0x1000 0x129000 0x1000>;
  266. };
  267. dcsr-cpu-sb-proxy@130000 {
  268. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  269. cpu-handle = <&cpu6>;
  270. reg = <0x130000 0x1000 0x131000 0x1000>;
  271. };
  272. dcsr-cpu-sb-proxy@138000 {
  273. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  274. cpu-handle = <&cpu7>;
  275. reg = <0x138000 0x1000 0x139000 0x1000>;
  276. };
  277. dcsr-cpu-sb-proxy@140000 {
  278. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  279. cpu-handle = <&cpu8>;
  280. reg = <0x140000 0x1000 0x141000 0x1000>;
  281. };
  282. dcsr-cpu-sb-proxy@148000 {
  283. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  284. cpu-handle = <&cpu9>;
  285. reg = <0x148000 0x1000 0x149000 0x1000>;
  286. };
  287. dcsr-cpu-sb-proxy@150000 {
  288. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  289. cpu-handle = <&cpu10>;
  290. reg = <0x150000 0x1000 0x151000 0x1000>;
  291. };
  292. dcsr-cpu-sb-proxy@158000 {
  293. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  294. cpu-handle = <&cpu11>;
  295. reg = <0x158000 0x1000 0x159000 0x1000>;
  296. };
  297. };
  298. &bportals {
  299. #address-cells = <0x1>;
  300. #size-cells = <0x1>;
  301. compatible = "simple-bus";
  302. bman-portal@0 {
  303. compatible = "fsl,bman-portal";
  304. reg = <0x0 0x4000>, <0x1000000 0x1000>;
  305. interrupts = <105 2 0 0>;
  306. };
  307. bman-portal@4000 {
  308. compatible = "fsl,bman-portal";
  309. reg = <0x4000 0x4000>, <0x1001000 0x1000>;
  310. interrupts = <107 2 0 0>;
  311. };
  312. bman-portal@8000 {
  313. compatible = "fsl,bman-portal";
  314. reg = <0x8000 0x4000>, <0x1002000 0x1000>;
  315. interrupts = <109 2 0 0>;
  316. };
  317. bman-portal@c000 {
  318. compatible = "fsl,bman-portal";
  319. reg = <0xc000 0x4000>, <0x1003000 0x1000>;
  320. interrupts = <111 2 0 0>;
  321. };
  322. bman-portal@10000 {
  323. compatible = "fsl,bman-portal";
  324. reg = <0x10000 0x4000>, <0x1004000 0x1000>;
  325. interrupts = <113 2 0 0>;
  326. };
  327. bman-portal@14000 {
  328. compatible = "fsl,bman-portal";
  329. reg = <0x14000 0x4000>, <0x1005000 0x1000>;
  330. interrupts = <115 2 0 0>;
  331. };
  332. bman-portal@18000 {
  333. compatible = "fsl,bman-portal";
  334. reg = <0x18000 0x4000>, <0x1006000 0x1000>;
  335. interrupts = <117 2 0 0>;
  336. };
  337. bman-portal@1c000 {
  338. compatible = "fsl,bman-portal";
  339. reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
  340. interrupts = <119 2 0 0>;
  341. };
  342. bman-portal@20000 {
  343. compatible = "fsl,bman-portal";
  344. reg = <0x20000 0x4000>, <0x1008000 0x1000>;
  345. interrupts = <121 2 0 0>;
  346. };
  347. bman-portal@24000 {
  348. compatible = "fsl,bman-portal";
  349. reg = <0x24000 0x4000>, <0x1009000 0x1000>;
  350. interrupts = <123 2 0 0>;
  351. };
  352. bman-portal@28000 {
  353. compatible = "fsl,bman-portal";
  354. reg = <0x28000 0x4000>, <0x100a000 0x1000>;
  355. interrupts = <125 2 0 0>;
  356. };
  357. bman-portal@2c000 {
  358. compatible = "fsl,bman-portal";
  359. reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
  360. interrupts = <127 2 0 0>;
  361. };
  362. bman-portal@30000 {
  363. compatible = "fsl,bman-portal";
  364. reg = <0x30000 0x4000>, <0x100c000 0x1000>;
  365. interrupts = <129 2 0 0>;
  366. };
  367. bman-portal@34000 {
  368. compatible = "fsl,bman-portal";
  369. reg = <0x34000 0x4000>, <0x100d000 0x1000>;
  370. interrupts = <131 2 0 0>;
  371. };
  372. bman-portal@38000 {
  373. compatible = "fsl,bman-portal";
  374. reg = <0x38000 0x4000>, <0x100e000 0x1000>;
  375. interrupts = <133 2 0 0>;
  376. };
  377. bman-portal@3c000 {
  378. compatible = "fsl,bman-portal";
  379. reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
  380. interrupts = <135 2 0 0>;
  381. };
  382. bman-portal@40000 {
  383. compatible = "fsl,bman-portal";
  384. reg = <0x40000 0x4000>, <0x1010000 0x1000>;
  385. interrupts = <137 2 0 0>;
  386. };
  387. bman-portal@44000 {
  388. compatible = "fsl,bman-portal";
  389. reg = <0x44000 0x4000>, <0x1011000 0x1000>;
  390. interrupts = <139 2 0 0>;
  391. };
  392. bman-portal@48000 {
  393. compatible = "fsl,bman-portal";
  394. reg = <0x48000 0x4000>, <0x1012000 0x1000>;
  395. interrupts = <141 2 0 0>;
  396. };
  397. bman-portal@4c000 {
  398. compatible = "fsl,bman-portal";
  399. reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
  400. interrupts = <143 2 0 0>;
  401. };
  402. bman-portal@50000 {
  403. compatible = "fsl,bman-portal";
  404. reg = <0x50000 0x4000>, <0x1014000 0x1000>;
  405. interrupts = <145 2 0 0>;
  406. };
  407. bman-portal@54000 {
  408. compatible = "fsl,bman-portal";
  409. reg = <0x54000 0x4000>, <0x1015000 0x1000>;
  410. interrupts = <147 2 0 0>;
  411. };
  412. bman-portal@58000 {
  413. compatible = "fsl,bman-portal";
  414. reg = <0x58000 0x4000>, <0x1016000 0x1000>;
  415. interrupts = <149 2 0 0>;
  416. };
  417. bman-portal@5c000 {
  418. compatible = "fsl,bman-portal";
  419. reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
  420. interrupts = <151 2 0 0>;
  421. };
  422. bman-portal@60000 {
  423. compatible = "fsl,bman-portal";
  424. reg = <0x60000 0x4000>, <0x1018000 0x1000>;
  425. interrupts = <153 2 0 0>;
  426. };
  427. bman-portal@64000 {
  428. compatible = "fsl,bman-portal";
  429. reg = <0x64000 0x4000>, <0x1019000 0x1000>;
  430. interrupts = <155 2 0 0>;
  431. };
  432. bman-portal@68000 {
  433. compatible = "fsl,bman-portal";
  434. reg = <0x68000 0x4000>, <0x101a000 0x1000>;
  435. interrupts = <157 2 0 0>;
  436. };
  437. bman-portal@6c000 {
  438. compatible = "fsl,bman-portal";
  439. reg = <0x6c000 0x4000>, <0x101b000 0x1000>;
  440. interrupts = <159 2 0 0>;
  441. };
  442. bman-portal@70000 {
  443. compatible = "fsl,bman-portal";
  444. reg = <0x70000 0x4000>, <0x101c000 0x1000>;
  445. interrupts = <161 2 0 0>;
  446. };
  447. bman-portal@74000 {
  448. compatible = "fsl,bman-portal";
  449. reg = <0x74000 0x4000>, <0x101d000 0x1000>;
  450. interrupts = <163 2 0 0>;
  451. };
  452. bman-portal@78000 {
  453. compatible = "fsl,bman-portal";
  454. reg = <0x78000 0x4000>, <0x101e000 0x1000>;
  455. interrupts = <165 2 0 0>;
  456. };
  457. bman-portal@7c000 {
  458. compatible = "fsl,bman-portal";
  459. reg = <0x7c000 0x4000>, <0x101f000 0x1000>;
  460. interrupts = <167 2 0 0>;
  461. };
  462. bman-portal@80000 {
  463. compatible = "fsl,bman-portal";
  464. reg = <0x80000 0x4000>, <0x1020000 0x1000>;
  465. interrupts = <169 2 0 0>;
  466. };
  467. bman-portal@84000 {
  468. compatible = "fsl,bman-portal";
  469. reg = <0x84000 0x4000>, <0x1021000 0x1000>;
  470. interrupts = <171 2 0 0>;
  471. };
  472. bman-portal@88000 {
  473. compatible = "fsl,bman-portal";
  474. reg = <0x88000 0x4000>, <0x1022000 0x1000>;
  475. interrupts = <173 2 0 0>;
  476. };
  477. bman-portal@8c000 {
  478. compatible = "fsl,bman-portal";
  479. reg = <0x8c000 0x4000>, <0x1023000 0x1000>;
  480. interrupts = <175 2 0 0>;
  481. };
  482. bman-portal@90000 {
  483. compatible = "fsl,bman-portal";
  484. reg = <0x90000 0x4000>, <0x1024000 0x1000>;
  485. interrupts = <385 2 0 0>;
  486. };
  487. bman-portal@94000 {
  488. compatible = "fsl,bman-portal";
  489. reg = <0x94000 0x4000>, <0x1025000 0x1000>;
  490. interrupts = <387 2 0 0>;
  491. };
  492. bman-portal@98000 {
  493. compatible = "fsl,bman-portal";
  494. reg = <0x98000 0x4000>, <0x1026000 0x1000>;
  495. interrupts = <389 2 0 0>;
  496. };
  497. bman-portal@9c000 {
  498. compatible = "fsl,bman-portal";
  499. reg = <0x9c000 0x4000>, <0x1027000 0x1000>;
  500. interrupts = <391 2 0 0>;
  501. };
  502. bman-portal@a0000 {
  503. compatible = "fsl,bman-portal";
  504. reg = <0xa0000 0x4000>, <0x1028000 0x1000>;
  505. interrupts = <393 2 0 0>;
  506. };
  507. bman-portal@a4000 {
  508. compatible = "fsl,bman-portal";
  509. reg = <0xa4000 0x4000>, <0x1029000 0x1000>;
  510. interrupts = <395 2 0 0>;
  511. };
  512. bman-portal@a8000 {
  513. compatible = "fsl,bman-portal";
  514. reg = <0xa8000 0x4000>, <0x102a000 0x1000>;
  515. interrupts = <397 2 0 0>;
  516. };
  517. bman-portal@ac000 {
  518. compatible = "fsl,bman-portal";
  519. reg = <0xac000 0x4000>, <0x102b000 0x1000>;
  520. interrupts = <399 2 0 0>;
  521. };
  522. bman-portal@b0000 {
  523. compatible = "fsl,bman-portal";
  524. reg = <0xb0000 0x4000>, <0x102c000 0x1000>;
  525. interrupts = <401 2 0 0>;
  526. };
  527. bman-portal@b4000 {
  528. compatible = "fsl,bman-portal";
  529. reg = <0xb4000 0x4000>, <0x102d000 0x1000>;
  530. interrupts = <403 2 0 0>;
  531. };
  532. bman-portal@b8000 {
  533. compatible = "fsl,bman-portal";
  534. reg = <0xb8000 0x4000>, <0x102e000 0x1000>;
  535. interrupts = <405 2 0 0>;
  536. };
  537. bman-portal@bc000 {
  538. compatible = "fsl,bman-portal";
  539. reg = <0xbc000 0x4000>, <0x102f000 0x1000>;
  540. interrupts = <407 2 0 0>;
  541. };
  542. bman-portal@c0000 {
  543. compatible = "fsl,bman-portal";
  544. reg = <0xc0000 0x4000>, <0x1030000 0x1000>;
  545. interrupts = <409 2 0 0>;
  546. };
  547. bman-portal@c4000 {
  548. compatible = "fsl,bman-portal";
  549. reg = <0xc4000 0x4000>, <0x1031000 0x1000>;
  550. interrupts = <411 2 0 0>;
  551. };
  552. };
  553. &qportals {
  554. #address-cells = <0x1>;
  555. #size-cells = <0x1>;
  556. compatible = "simple-bus";
  557. qportal0: qman-portal@0 {
  558. compatible = "fsl,qman-portal";
  559. reg = <0x0 0x4000>, <0x1000000 0x1000>;
  560. interrupts = <104 0x2 0 0>;
  561. cell-index = <0x0>;
  562. };
  563. qportal1: qman-portal@4000 {
  564. compatible = "fsl,qman-portal";
  565. reg = <0x4000 0x4000>, <0x1001000 0x1000>;
  566. interrupts = <106 0x2 0 0>;
  567. cell-index = <0x1>;
  568. };
  569. qportal2: qman-portal@8000 {
  570. compatible = "fsl,qman-portal";
  571. reg = <0x8000 0x4000>, <0x1002000 0x1000>;
  572. interrupts = <108 0x2 0 0>;
  573. cell-index = <0x2>;
  574. };
  575. qportal3: qman-portal@c000 {
  576. compatible = "fsl,qman-portal";
  577. reg = <0xc000 0x4000>, <0x1003000 0x1000>;
  578. interrupts = <110 0x2 0 0>;
  579. cell-index = <0x3>;
  580. };
  581. qportal4: qman-portal@10000 {
  582. compatible = "fsl,qman-portal";
  583. reg = <0x10000 0x4000>, <0x1004000 0x1000>;
  584. interrupts = <112 0x2 0 0>;
  585. cell-index = <0x4>;
  586. };
  587. qportal5: qman-portal@14000 {
  588. compatible = "fsl,qman-portal";
  589. reg = <0x14000 0x4000>, <0x1005000 0x1000>;
  590. interrupts = <114 0x2 0 0>;
  591. cell-index = <0x5>;
  592. };
  593. qportal6: qman-portal@18000 {
  594. compatible = "fsl,qman-portal";
  595. reg = <0x18000 0x4000>, <0x1006000 0x1000>;
  596. interrupts = <116 0x2 0 0>;
  597. cell-index = <0x6>;
  598. };
  599. qportal7: qman-portal@1c000 {
  600. compatible = "fsl,qman-portal";
  601. reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
  602. interrupts = <118 0x2 0 0>;
  603. cell-index = <0x7>;
  604. };
  605. qportal8: qman-portal@20000 {
  606. compatible = "fsl,qman-portal";
  607. reg = <0x20000 0x4000>, <0x1008000 0x1000>;
  608. interrupts = <120 0x2 0 0>;
  609. cell-index = <0x8>;
  610. };
  611. qportal9: qman-portal@24000 {
  612. compatible = "fsl,qman-portal";
  613. reg = <0x24000 0x4000>, <0x1009000 0x1000>;
  614. interrupts = <122 0x2 0 0>;
  615. cell-index = <0x9>;
  616. };
  617. qportal10: qman-portal@28000 {
  618. compatible = "fsl,qman-portal";
  619. reg = <0x28000 0x4000>, <0x100a000 0x1000>;
  620. interrupts = <124 0x2 0 0>;
  621. cell-index = <0xa>;
  622. };
  623. qportal11: qman-portal@2c000 {
  624. compatible = "fsl,qman-portal";
  625. reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
  626. interrupts = <126 0x2 0 0>;
  627. cell-index = <0xb>;
  628. };
  629. qportal12: qman-portal@30000 {
  630. compatible = "fsl,qman-portal";
  631. reg = <0x30000 0x4000>, <0x100c000 0x1000>;
  632. interrupts = <128 0x2 0 0>;
  633. cell-index = <0xc>;
  634. };
  635. qportal13: qman-portal@34000 {
  636. compatible = "fsl,qman-portal";
  637. reg = <0x34000 0x4000>, <0x100d000 0x1000>;
  638. interrupts = <130 0x2 0 0>;
  639. cell-index = <0xd>;
  640. };
  641. qportal14: qman-portal@38000 {
  642. compatible = "fsl,qman-portal";
  643. reg = <0x38000 0x4000>, <0x100e000 0x1000>;
  644. interrupts = <132 0x2 0 0>;
  645. cell-index = <0xe>;
  646. };
  647. qportal15: qman-portal@3c000 {
  648. compatible = "fsl,qman-portal";
  649. reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
  650. interrupts = <134 0x2 0 0>;
  651. cell-index = <0xf>;
  652. };
  653. qportal16: qman-portal@40000 {
  654. compatible = "fsl,qman-portal";
  655. reg = <0x40000 0x4000>, <0x1010000 0x1000>;
  656. interrupts = <136 0x2 0 0>;
  657. cell-index = <0x10>;
  658. };
  659. qportal17: qman-portal@44000 {
  660. compatible = "fsl,qman-portal";
  661. reg = <0x44000 0x4000>, <0x1011000 0x1000>;
  662. interrupts = <138 0x2 0 0>;
  663. cell-index = <0x11>;
  664. };
  665. qportal18: qman-portal@48000 {
  666. compatible = "fsl,qman-portal";
  667. reg = <0x48000 0x4000>, <0x1012000 0x1000>;
  668. interrupts = <140 0x2 0 0>;
  669. cell-index = <0x12>;
  670. };
  671. qportal19: qman-portal@4c000 {
  672. compatible = "fsl,qman-portal";
  673. reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
  674. interrupts = <142 0x2 0 0>;
  675. cell-index = <0x13>;
  676. };
  677. qportal20: qman-portal@50000 {
  678. compatible = "fsl,qman-portal";
  679. reg = <0x50000 0x4000>, <0x1014000 0x1000>;
  680. interrupts = <144 0x2 0 0>;
  681. cell-index = <0x14>;
  682. };
  683. qportal21: qman-portal@54000 {
  684. compatible = "fsl,qman-portal";
  685. reg = <0x54000 0x4000>, <0x1015000 0x1000>;
  686. interrupts = <146 0x2 0 0>;
  687. cell-index = <0x15>;
  688. };
  689. qportal22: qman-portal@58000 {
  690. compatible = "fsl,qman-portal";
  691. reg = <0x58000 0x4000>, <0x1016000 0x1000>;
  692. interrupts = <148 0x2 0 0>;
  693. cell-index = <0x16>;
  694. };
  695. qportal23: qman-portal@5c000 {
  696. compatible = "fsl,qman-portal";
  697. reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
  698. interrupts = <150 0x2 0 0>;
  699. cell-index = <0x17>;
  700. };
  701. qportal24: qman-portal@60000 {
  702. compatible = "fsl,qman-portal";
  703. reg = <0x60000 0x4000>, <0x1018000 0x1000>;
  704. interrupts = <152 0x2 0 0>;
  705. cell-index = <0x18>;
  706. };
  707. qportal25: qman-portal@64000 {
  708. compatible = "fsl,qman-portal";
  709. reg = <0x64000 0x4000>, <0x1019000 0x1000>;
  710. interrupts = <154 0x2 0 0>;
  711. cell-index = <0x19>;
  712. };
  713. qportal26: qman-portal@68000 {
  714. compatible = "fsl,qman-portal";
  715. reg = <0x68000 0x4000>, <0x101a000 0x1000>;
  716. interrupts = <156 0x2 0 0>;
  717. cell-index = <0x1a>;
  718. };
  719. qportal27: qman-portal@6c000 {
  720. compatible = "fsl,qman-portal";
  721. reg = <0x6c000 0x4000>, <0x101b000 0x1000>;
  722. interrupts = <158 0x2 0 0>;
  723. cell-index = <0x1b>;
  724. };
  725. qportal28: qman-portal@70000 {
  726. compatible = "fsl,qman-portal";
  727. reg = <0x70000 0x4000>, <0x101c000 0x1000>;
  728. interrupts = <160 0x2 0 0>;
  729. cell-index = <0x1c>;
  730. };
  731. qportal29: qman-portal@74000 {
  732. compatible = "fsl,qman-portal";
  733. reg = <0x74000 0x4000>, <0x101d000 0x1000>;
  734. interrupts = <162 0x2 0 0>;
  735. cell-index = <0x1d>;
  736. };
  737. qportal30: qman-portal@78000 {
  738. compatible = "fsl,qman-portal";
  739. reg = <0x78000 0x4000>, <0x101e000 0x1000>;
  740. interrupts = <164 0x2 0 0>;
  741. cell-index = <0x1e>;
  742. };
  743. qportal31: qman-portal@7c000 {
  744. compatible = "fsl,qman-portal";
  745. reg = <0x7c000 0x4000>, <0x101f000 0x1000>;
  746. interrupts = <166 0x2 0 0>;
  747. cell-index = <0x1f>;
  748. };
  749. qportal32: qman-portal@80000 {
  750. compatible = "fsl,qman-portal";
  751. reg = <0x80000 0x4000>, <0x1020000 0x1000>;
  752. interrupts = <168 0x2 0 0>;
  753. cell-index = <0x20>;
  754. };
  755. qportal33: qman-portal@84000 {
  756. compatible = "fsl,qman-portal";
  757. reg = <0x84000 0x4000>, <0x1021000 0x1000>;
  758. interrupts = <170 0x2 0 0>;
  759. cell-index = <0x21>;
  760. };
  761. qportal34: qman-portal@88000 {
  762. compatible = "fsl,qman-portal";
  763. reg = <0x88000 0x4000>, <0x1022000 0x1000>;
  764. interrupts = <172 0x2 0 0>;
  765. cell-index = <0x22>;
  766. };
  767. qportal35: qman-portal@8c000 {
  768. compatible = "fsl,qman-portal";
  769. reg = <0x8c000 0x4000>, <0x1023000 0x1000>;
  770. interrupts = <174 0x2 0 0>;
  771. cell-index = <0x23>;
  772. };
  773. qportal36: qman-portal@90000 {
  774. compatible = "fsl,qman-portal";
  775. reg = <0x90000 0x4000>, <0x1024000 0x1000>;
  776. interrupts = <384 0x2 0 0>;
  777. cell-index = <0x24>;
  778. };
  779. qportal37: qman-portal@94000 {
  780. compatible = "fsl,qman-portal";
  781. reg = <0x94000 0x4000>, <0x1025000 0x1000>;
  782. interrupts = <386 0x2 0 0>;
  783. cell-index = <0x25>;
  784. };
  785. qportal38: qman-portal@98000 {
  786. compatible = "fsl,qman-portal";
  787. reg = <0x98000 0x4000>, <0x1026000 0x1000>;
  788. interrupts = <388 0x2 0 0>;
  789. cell-index = <0x26>;
  790. };
  791. qportal39: qman-portal@9c000 {
  792. compatible = "fsl,qman-portal";
  793. reg = <0x9c000 0x4000>, <0x1027000 0x1000>;
  794. interrupts = <390 0x2 0 0>;
  795. cell-index = <0x27>;
  796. };
  797. qportal40: qman-portal@a0000 {
  798. compatible = "fsl,qman-portal";
  799. reg = <0xa0000 0x4000>, <0x1028000 0x1000>;
  800. interrupts = <392 0x2 0 0>;
  801. cell-index = <0x28>;
  802. };
  803. qportal41: qman-portal@a4000 {
  804. compatible = "fsl,qman-portal";
  805. reg = <0xa4000 0x4000>, <0x1029000 0x1000>;
  806. interrupts = <394 0x2 0 0>;
  807. cell-index = <0x29>;
  808. };
  809. qportal42: qman-portal@a8000 {
  810. compatible = "fsl,qman-portal";
  811. reg = <0xa8000 0x4000>, <0x102a000 0x1000>;
  812. interrupts = <396 0x2 0 0>;
  813. cell-index = <0x2a>;
  814. };
  815. qportal43: qman-portal@ac000 {
  816. compatible = "fsl,qman-portal";
  817. reg = <0xac000 0x4000>, <0x102b000 0x1000>;
  818. interrupts = <398 0x2 0 0>;
  819. cell-index = <0x2b>;
  820. };
  821. qportal44: qman-portal@b0000 {
  822. compatible = "fsl,qman-portal";
  823. reg = <0xb0000 0x4000>, <0x102c000 0x1000>;
  824. interrupts = <400 0x2 0 0>;
  825. cell-index = <0x2c>;
  826. };
  827. qportal45: qman-portal@b4000 {
  828. compatible = "fsl,qman-portal";
  829. reg = <0xb4000 0x4000>, <0x102d000 0x1000>;
  830. interrupts = <402 0x2 0 0>;
  831. cell-index = <0x2d>;
  832. };
  833. qportal46: qman-portal@b8000 {
  834. compatible = "fsl,qman-portal";
  835. reg = <0xb8000 0x4000>, <0x102e000 0x1000>;
  836. interrupts = <404 0x2 0 0>;
  837. cell-index = <0x2e>;
  838. };
  839. qportal47: qman-portal@bc000 {
  840. compatible = "fsl,qman-portal";
  841. reg = <0xbc000 0x4000>, <0x102f000 0x1000>;
  842. interrupts = <406 0x2 0 0>;
  843. cell-index = <0x2f>;
  844. };
  845. qportal48: qman-portal@c0000 {
  846. compatible = "fsl,qman-portal";
  847. reg = <0xc0000 0x4000>, <0x1030000 0x1000>;
  848. interrupts = <408 0x2 0 0>;
  849. cell-index = <0x30>;
  850. };
  851. qportal49: qman-portal@c4000 {
  852. compatible = "fsl,qman-portal";
  853. reg = <0xc4000 0x4000>, <0x1031000 0x1000>;
  854. interrupts = <410 0x2 0 0>;
  855. cell-index = <0x31>;
  856. };
  857. };
  858. &soc {
  859. #address-cells = <1>;
  860. #size-cells = <1>;
  861. device_type = "soc";
  862. compatible = "simple-bus";
  863. soc-sram-error {
  864. compatible = "fsl,soc-sram-error";
  865. interrupts = <16 2 1 29>;
  866. };
  867. corenet-law@0 {
  868. compatible = "fsl,corenet-law";
  869. reg = <0x0 0x1000>;
  870. fsl,num-laws = <32>;
  871. };
  872. ddr1: memory-controller@8000 {
  873. compatible = "fsl,qoriq-memory-controller-v4.7",
  874. "fsl,qoriq-memory-controller";
  875. reg = <0x8000 0x1000>;
  876. interrupts = <16 2 1 23>;
  877. };
  878. ddr2: memory-controller@9000 {
  879. compatible = "fsl,qoriq-memory-controller-v4.7",
  880. "fsl,qoriq-memory-controller";
  881. reg = <0x9000 0x1000>;
  882. interrupts = <16 2 1 22>;
  883. };
  884. ddr3: memory-controller@a000 {
  885. compatible = "fsl,qoriq-memory-controller-v4.7",
  886. "fsl,qoriq-memory-controller";
  887. reg = <0xa000 0x1000>;
  888. interrupts = <16 2 1 21>;
  889. };
  890. cpc: l3-cache-controller@10000 {
  891. compatible = "fsl,t4240-l3-cache-controller", "cache";
  892. reg = <0x10000 0x1000
  893. 0x11000 0x1000
  894. 0x12000 0x1000>;
  895. interrupts = <16 2 1 27
  896. 16 2 1 26
  897. 16 2 1 25>;
  898. };
  899. corenet-cf@18000 {
  900. compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
  901. reg = <0x18000 0x1000>;
  902. interrupts = <16 2 1 31>;
  903. fsl,ccf-num-csdids = <32>;
  904. fsl,ccf-num-snoopids = <32>;
  905. };
  906. iommu@20000 {
  907. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  908. reg = <0x20000 0x6000>;
  909. fsl,portid-mapping = <0x8000>;
  910. interrupts = <
  911. 24 2 0 0
  912. 16 2 1 30>;
  913. };
  914. /include/ "qoriq-mpic4.3.dtsi"
  915. guts: global-utilities@e0000 {
  916. compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
  917. reg = <0xe0000 0xe00>;
  918. fsl,has-rstcr;
  919. fsl,liodn-bits = <12>;
  920. };
  921. /include/ "qoriq-clockgen2.dtsi"
  922. global-utilities@e1000 {
  923. compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
  924. };
  925. rcpm: global-utilities@e2000 {
  926. compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
  927. reg = <0xe2000 0x1000>;
  928. };
  929. sfp: sfp@e8000 {
  930. compatible = "fsl,t4240-sfp";
  931. reg = <0xe8000 0x1000>;
  932. };
  933. serdes: serdes@ea000 {
  934. compatible = "fsl,t4240-serdes";
  935. reg = <0xea000 0x4000>;
  936. };
  937. /include/ "elo3-dma-0.dtsi"
  938. /include/ "elo3-dma-1.dtsi"
  939. /include/ "elo3-dma-2.dtsi"
  940. /include/ "qoriq-espi-0.dtsi"
  941. spi@110000 {
  942. fsl,espi-num-chipselects = <4>;
  943. };
  944. /include/ "qoriq-esdhc-0.dtsi"
  945. sdhc@114000 {
  946. compatible = "fsl,t4240-esdhc", "fsl,esdhc";
  947. sdhci,auto-cmd12;
  948. };
  949. /include/ "qoriq-i2c-0.dtsi"
  950. /include/ "qoriq-i2c-1.dtsi"
  951. /include/ "qoriq-duart-0.dtsi"
  952. /include/ "qoriq-duart-1.dtsi"
  953. /include/ "qoriq-gpio-0.dtsi"
  954. /include/ "qoriq-gpio-1.dtsi"
  955. /include/ "qoriq-gpio-2.dtsi"
  956. /include/ "qoriq-gpio-3.dtsi"
  957. /include/ "qoriq-usb2-mph-0.dtsi"
  958. usb0: usb@210000 {
  959. compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
  960. phy_type = "utmi";
  961. port0;
  962. };
  963. /include/ "qoriq-usb2-dr-0.dtsi"
  964. usb1: usb@211000 {
  965. compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
  966. dr_mode = "host";
  967. phy_type = "utmi";
  968. };
  969. /include/ "qoriq-sata2-0.dtsi"
  970. /include/ "qoriq-sata2-1.dtsi"
  971. /include/ "qoriq-sec5.0-0.dtsi"
  972. /include/ "qoriq-qman3.dtsi"
  973. /include/ "qoriq-bman1.dtsi"
  974. /include/ "qoriq-fman3-0.dtsi"
  975. /include/ "qoriq-fman3-0-1g-0.dtsi"
  976. /include/ "qoriq-fman3-0-1g-1.dtsi"
  977. /include/ "qoriq-fman3-0-1g-2.dtsi"
  978. /include/ "qoriq-fman3-0-1g-3.dtsi"
  979. /include/ "qoriq-fman3-0-1g-4.dtsi"
  980. /include/ "qoriq-fman3-0-1g-5.dtsi"
  981. /include/ "qoriq-fman3-0-10g-0.dtsi"
  982. /include/ "qoriq-fman3-0-10g-1.dtsi"
  983. fman@400000 {
  984. enet0: ethernet@e0000 {
  985. };
  986. enet1: ethernet@e2000 {
  987. };
  988. enet2: ethernet@e4000 {
  989. };
  990. enet3: ethernet@e6000 {
  991. };
  992. enet4: ethernet@e8000 {
  993. };
  994. enet5: ethernet@ea000 {
  995. };
  996. enet6: ethernet@f0000 {
  997. };
  998. enet7: ethernet@f2000 {
  999. };
  1000. mdio@fc000 {
  1001. status = "disabled";
  1002. };
  1003. mdio@fd000 {
  1004. status = "disabled";
  1005. };
  1006. };
  1007. /include/ "qoriq-fman3-1.dtsi"
  1008. /include/ "qoriq-fman3-1-1g-0.dtsi"
  1009. /include/ "qoriq-fman3-1-1g-1.dtsi"
  1010. /include/ "qoriq-fman3-1-1g-2.dtsi"
  1011. /include/ "qoriq-fman3-1-1g-3.dtsi"
  1012. /include/ "qoriq-fman3-1-1g-4.dtsi"
  1013. /include/ "qoriq-fman3-1-1g-5.dtsi"
  1014. /include/ "qoriq-fman3-1-10g-0.dtsi"
  1015. /include/ "qoriq-fman3-1-10g-1.dtsi"
  1016. fman@500000 {
  1017. enet8: ethernet@e0000 {
  1018. };
  1019. enet9: ethernet@e2000 {
  1020. };
  1021. enet10: ethernet@e4000 {
  1022. };
  1023. enet11: ethernet@e6000 {
  1024. };
  1025. enet12: ethernet@e8000 {
  1026. };
  1027. enet13: ethernet@ea000 {
  1028. };
  1029. enet14: ethernet@f0000 {
  1030. };
  1031. enet15: ethernet@f2000 {
  1032. };
  1033. mdio@fc000 {
  1034. interrupts = <100 1 0 0>;
  1035. };
  1036. mdio@fd000 {
  1037. interrupts = <101 1 0 0>;
  1038. };
  1039. };
  1040. L2_1: l2-cache-controller@c20000 {
  1041. compatible = "fsl,t4240-l2-cache-controller";
  1042. reg = <0xc20000 0x40000>;
  1043. next-level-cache = <&cpc>;
  1044. };
  1045. L2_2: l2-cache-controller@c60000 {
  1046. compatible = "fsl,t4240-l2-cache-controller";
  1047. reg = <0xc60000 0x40000>;
  1048. next-level-cache = <&cpc>;
  1049. };
  1050. L2_3: l2-cache-controller@ca0000 {
  1051. compatible = "fsl,t4240-l2-cache-controller";
  1052. reg = <0xca0000 0x40000>;
  1053. next-level-cache = <&cpc>;
  1054. };
  1055. };