ppa8548.dts 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * PPA8548 Device Tree Source (36-bit address map)
  4. * Copyright 2013 Prodrive B.V.
  5. *
  6. * Based on:
  7. * MPC8548 CDS Device Tree Source (36-bit address map)
  8. * Copyright 2012 Freescale Semiconductor Inc.
  9. */
  10. /include/ "mpc8548si-pre.dtsi"
  11. / {
  12. model = "ppa8548";
  13. compatible = "ppa8548";
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. interrupt-parent = <&mpic>;
  17. memory {
  18. device_type = "memory";
  19. reg = <0 0 0x0 0x40000000>;
  20. };
  21. lbc: localbus@fe0005000 {
  22. reg = <0xf 0xe0005000 0 0x1000>;
  23. ranges = <0x0 0x0 0xf 0xff800000 0x00800000>;
  24. };
  25. soc: soc8548@fe0000000 {
  26. ranges = <0 0xf 0xe0000000 0x100000>;
  27. };
  28. pci0: pci@fe0008000 {
  29. /* ppa8548 board doesn't support PCI */
  30. status = "disabled";
  31. };
  32. pci1: pci@fe0009000 {
  33. /* ppa8548 board doesn't support PCI */
  34. status = "disabled";
  35. };
  36. pci2: pcie@fe000a000 {
  37. /* ppa8548 board doesn't support PCI */
  38. status = "disabled";
  39. };
  40. rio: rapidio@fe00c0000 {
  41. reg = <0xf 0xe00c0000 0x0 0x11000>;
  42. port1 {
  43. ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>;
  44. };
  45. };
  46. };
  47. &lbc {
  48. nor@0 {
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. compatible = "cfi-flash";
  52. reg = <0x0 0x0 0x00800000>;
  53. bank-width = <2>;
  54. device-width = <2>;
  55. partition@0 {
  56. reg = <0x0 0x7A0000>;
  57. label = "user";
  58. };
  59. partition@7A0000 {
  60. reg = <0x7A0000 0x20000>;
  61. label = "env";
  62. read-only;
  63. };
  64. partition@7C0000 {
  65. reg = <0x7C0000 0x40000>;
  66. label = "u-boot";
  67. read-only;
  68. };
  69. };
  70. };
  71. &soc {
  72. i2c@3000 {
  73. rtc@6f {
  74. compatible = "intersil,isl1208";
  75. reg = <0x6f>;
  76. };
  77. };
  78. i2c@3100 {
  79. };
  80. /*
  81. * Only ethernet controller @25000 and @26000 are used.
  82. * Use alias enet2 and enet3 for the remainig controllers,
  83. * to stay compatible with mpc8548si-pre.dtsi.
  84. */
  85. enet2: ethernet@24000 {
  86. status = "disabled";
  87. };
  88. mdio@24520 {
  89. phy0: ethernet-phy@0 {
  90. interrupts = <7 1 0 0>;
  91. reg = <0x0>;
  92. };
  93. phy1: ethernet-phy@1 {
  94. interrupts = <8 1 0 0>;
  95. reg = <0x1>;
  96. };
  97. tbi0: tbi-phy@11 {
  98. reg = <0x11>;
  99. device_type = "tbi-phy";
  100. };
  101. };
  102. enet0: ethernet@25000 {
  103. tbi-handle = <&tbi1>;
  104. phy-handle = <&phy0>;
  105. };
  106. mdio@25520 {
  107. tbi1: tbi-phy@11 {
  108. reg = <0x11>;
  109. device_type = "tbi-phy";
  110. };
  111. };
  112. enet1: ethernet@26000 {
  113. tbi-handle = <&tbi2>;
  114. phy-handle = <&phy1>;
  115. };
  116. mdio@26520 {
  117. tbi2: tbi-phy@11 {
  118. reg = <0x11>;
  119. device_type = "tbi-phy";
  120. };
  121. };
  122. enet3: ethernet@27000 {
  123. status = "disabled";
  124. };
  125. mdio@27520 {
  126. tbi3: tbi-phy@11 {
  127. reg = <0x11>;
  128. device_type = "tbi-phy";
  129. };
  130. };
  131. crypto@30000 {
  132. status = "disabled";
  133. };
  134. };
  135. /include/ "mpc8548si-post.dtsi"