p4080si-post.dtsi 12 KB

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  1. /*
  2. * P4080/P4040 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 - 2015 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &bman_fbpr {
  35. compatible = "fsl,bman-fbpr";
  36. alloc-ranges = <0 0 0x10 0>;
  37. };
  38. &qman_fqd {
  39. compatible = "fsl,qman-fqd";
  40. alloc-ranges = <0 0 0x10 0>;
  41. };
  42. &qman_pfdr {
  43. compatible = "fsl,qman-pfdr";
  44. alloc-ranges = <0 0 0x10 0>;
  45. };
  46. &lbc {
  47. compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
  48. interrupts = <25 2 0 0>;
  49. #address-cells = <2>;
  50. #size-cells = <1>;
  51. };
  52. /* controller at 0x200000 */
  53. &pci0 {
  54. compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
  55. device_type = "pci";
  56. #size-cells = <2>;
  57. #address-cells = <3>;
  58. bus-range = <0x0 0xff>;
  59. clock-frequency = <33333333>;
  60. interrupts = <16 2 1 15>;
  61. fsl,iommu-parent = <&pamu0>;
  62. fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
  63. pcie@0 {
  64. reg = <0 0 0 0 0>;
  65. #interrupt-cells = <1>;
  66. #size-cells = <2>;
  67. #address-cells = <3>;
  68. device_type = "pci";
  69. interrupts = <16 2 1 15>;
  70. interrupt-map-mask = <0xf800 0 0 7>;
  71. interrupt-map = <
  72. /* IDSEL 0x0 */
  73. 0000 0 0 1 &mpic 40 1 0 0
  74. 0000 0 0 2 &mpic 1 1 0 0
  75. 0000 0 0 3 &mpic 2 1 0 0
  76. 0000 0 0 4 &mpic 3 1 0 0
  77. >;
  78. };
  79. };
  80. /* controller at 0x201000 */
  81. &pci1 {
  82. compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
  83. device_type = "pci";
  84. #size-cells = <2>;
  85. #address-cells = <3>;
  86. bus-range = <0 0xff>;
  87. clock-frequency = <33333333>;
  88. interrupts = <16 2 1 14>;
  89. fsl,iommu-parent = <&pamu0>;
  90. fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
  91. pcie@0 {
  92. reg = <0 0 0 0 0>;
  93. #interrupt-cells = <1>;
  94. #size-cells = <2>;
  95. #address-cells = <3>;
  96. device_type = "pci";
  97. interrupts = <16 2 1 14>;
  98. interrupt-map-mask = <0xf800 0 0 7>;
  99. interrupt-map = <
  100. /* IDSEL 0x0 */
  101. 0000 0 0 1 &mpic 41 1 0 0
  102. 0000 0 0 2 &mpic 5 1 0 0
  103. 0000 0 0 3 &mpic 6 1 0 0
  104. 0000 0 0 4 &mpic 7 1 0 0
  105. >;
  106. };
  107. };
  108. /* controller at 0x202000 */
  109. &pci2 {
  110. compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
  111. device_type = "pci";
  112. #size-cells = <2>;
  113. #address-cells = <3>;
  114. bus-range = <0x0 0xff>;
  115. clock-frequency = <33333333>;
  116. interrupts = <16 2 1 13>;
  117. fsl,iommu-parent = <&pamu0>;
  118. fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
  119. pcie@0 {
  120. reg = <0 0 0 0 0>;
  121. #interrupt-cells = <1>;
  122. #size-cells = <2>;
  123. #address-cells = <3>;
  124. device_type = "pci";
  125. interrupts = <16 2 1 13>;
  126. interrupt-map-mask = <0xf800 0 0 7>;
  127. interrupt-map = <
  128. /* IDSEL 0x0 */
  129. 0000 0 0 1 &mpic 42 1 0 0
  130. 0000 0 0 2 &mpic 9 1 0 0
  131. 0000 0 0 3 &mpic 10 1 0 0
  132. 0000 0 0 4 &mpic 11 1 0 0
  133. >;
  134. };
  135. };
  136. &rio {
  137. compatible = "fsl,srio";
  138. interrupts = <16 2 1 11>;
  139. #address-cells = <2>;
  140. #size-cells = <2>;
  141. fsl,srio-rmu-handle = <&rmu>;
  142. fsl,iommu-parent = <&pamu0>;
  143. ranges;
  144. port1 {
  145. #address-cells = <2>;
  146. #size-cells = <2>;
  147. cell-index = <1>;
  148. fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
  149. };
  150. port2 {
  151. #address-cells = <2>;
  152. #size-cells = <2>;
  153. cell-index = <2>;
  154. fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
  155. };
  156. };
  157. &dcsr {
  158. #address-cells = <1>;
  159. #size-cells = <1>;
  160. compatible = "fsl,dcsr", "simple-bus";
  161. dcsr-epu@0 {
  162. compatible = "fsl,p4080-dcsr-epu", "fsl,dcsr-epu";
  163. interrupts = <52 2 0 0
  164. 84 2 0 0
  165. 85 2 0 0>;
  166. reg = <0x0 0x1000>;
  167. };
  168. dcsr-npc {
  169. compatible = "fsl,dcsr-npc";
  170. reg = <0x1000 0x1000 0x1000000 0x8000>;
  171. };
  172. dcsr-nxc@2000 {
  173. compatible = "fsl,dcsr-nxc";
  174. reg = <0x2000 0x1000>;
  175. };
  176. dcsr-corenet {
  177. compatible = "fsl,dcsr-corenet";
  178. reg = <0x8000 0x1000 0xB0000 0x1000>;
  179. };
  180. dcsr-dpaa@9000 {
  181. compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
  182. reg = <0x9000 0x1000>;
  183. };
  184. dcsr-ocn@11000 {
  185. compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
  186. reg = <0x11000 0x1000>;
  187. };
  188. dcsr-ddr@12000 {
  189. compatible = "fsl,dcsr-ddr";
  190. dev-handle = <&ddr1>;
  191. reg = <0x12000 0x1000>;
  192. };
  193. dcsr-ddr@13000 {
  194. compatible = "fsl,dcsr-ddr";
  195. dev-handle = <&ddr2>;
  196. reg = <0x13000 0x1000>;
  197. };
  198. dcsr-nal@18000 {
  199. compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
  200. reg = <0x18000 0x1000>;
  201. };
  202. dcsr-rcpm@22000 {
  203. compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
  204. reg = <0x22000 0x1000>;
  205. };
  206. dcsr-cpu-sb-proxy@40000 {
  207. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  208. cpu-handle = <&cpu0>;
  209. reg = <0x40000 0x1000>;
  210. };
  211. dcsr-cpu-sb-proxy@41000 {
  212. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  213. cpu-handle = <&cpu1>;
  214. reg = <0x41000 0x1000>;
  215. };
  216. dcsr-cpu-sb-proxy@42000 {
  217. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  218. cpu-handle = <&cpu2>;
  219. reg = <0x42000 0x1000>;
  220. };
  221. dcsr-cpu-sb-proxy@43000 {
  222. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  223. cpu-handle = <&cpu3>;
  224. reg = <0x43000 0x1000>;
  225. };
  226. dcsr-cpu-sb-proxy@44000 {
  227. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  228. cpu-handle = <&cpu4>;
  229. reg = <0x44000 0x1000>;
  230. };
  231. dcsr-cpu-sb-proxy@45000 {
  232. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  233. cpu-handle = <&cpu5>;
  234. reg = <0x45000 0x1000>;
  235. };
  236. dcsr-cpu-sb-proxy@46000 {
  237. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  238. cpu-handle = <&cpu6>;
  239. reg = <0x46000 0x1000>;
  240. };
  241. dcsr-cpu-sb-proxy@47000 {
  242. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  243. cpu-handle = <&cpu7>;
  244. reg = <0x47000 0x1000>;
  245. };
  246. };
  247. /include/ "qoriq-bman1-portals.dtsi"
  248. /include/ "qoriq-qman1-portals.dtsi"
  249. &soc {
  250. #address-cells = <1>;
  251. #size-cells = <1>;
  252. device_type = "soc";
  253. compatible = "simple-bus";
  254. soc-sram-error {
  255. compatible = "fsl,soc-sram-error";
  256. interrupts = <16 2 1 29>;
  257. };
  258. corenet-law@0 {
  259. compatible = "fsl,corenet-law";
  260. reg = <0x0 0x1000>;
  261. fsl,num-laws = <32>;
  262. };
  263. ddr1: memory-controller@8000 {
  264. compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
  265. reg = <0x8000 0x1000>;
  266. interrupts = <16 2 1 23>;
  267. };
  268. ddr2: memory-controller@9000 {
  269. compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
  270. reg = <0x9000 0x1000>;
  271. interrupts = <16 2 1 22>;
  272. };
  273. cpc: l3-cache-controller@10000 {
  274. compatible = "fsl,p4080-l3-cache-controller", "cache";
  275. reg = <0x10000 0x1000
  276. 0x11000 0x1000>;
  277. interrupts = <16 2 1 27
  278. 16 2 1 26>;
  279. };
  280. corenet-cf@18000 {
  281. compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
  282. reg = <0x18000 0x1000>;
  283. interrupts = <16 2 1 31>;
  284. fsl,ccf-num-csdids = <32>;
  285. fsl,ccf-num-snoopids = <32>;
  286. };
  287. iommu@20000 {
  288. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  289. reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
  290. ranges = <0 0x20000 0x5000>;
  291. #address-cells = <1>;
  292. #size-cells = <1>;
  293. interrupts = <
  294. 24 2 0 0
  295. 16 2 1 30>;
  296. fsl,portid-mapping = <0x00f80000>;
  297. pamu0: pamu@0 {
  298. reg = <0 0x1000>;
  299. fsl,primary-cache-geometry = <32 1>;
  300. fsl,secondary-cache-geometry = <128 2>;
  301. };
  302. pamu1: pamu@1000 {
  303. reg = <0x1000 0x1000>;
  304. fsl,primary-cache-geometry = <32 1>;
  305. fsl,secondary-cache-geometry = <128 2>;
  306. };
  307. pamu2: pamu@2000 {
  308. reg = <0x2000 0x1000>;
  309. fsl,primary-cache-geometry = <32 1>;
  310. fsl,secondary-cache-geometry = <128 2>;
  311. };
  312. pamu3: pamu@3000 {
  313. reg = <0x3000 0x1000>;
  314. fsl,primary-cache-geometry = <32 1>;
  315. fsl,secondary-cache-geometry = <128 2>;
  316. };
  317. pamu4: pamu@4000 {
  318. reg = <0x4000 0x1000>;
  319. fsl,primary-cache-geometry = <32 1>;
  320. fsl,secondary-cache-geometry = <128 2>;
  321. };
  322. };
  323. /include/ "qoriq-rmu-0.dtsi"
  324. rmu@d3000 {
  325. fsl,iommu-parent = <&pamu0>;
  326. fsl,liodn-reg = <&guts 0x540>; /* RMULIODNR */
  327. };
  328. /include/ "qoriq-mpic.dtsi"
  329. guts: global-utilities@e0000 {
  330. compatible = "fsl,qoriq-device-config-1.0";
  331. reg = <0xe0000 0xe00>;
  332. fsl,has-rstcr;
  333. #sleep-cells = <1>;
  334. fsl,liodn-bits = <12>;
  335. };
  336. pins: global-utilities@e0e00 {
  337. compatible = "fsl,qoriq-pin-control-1.0";
  338. reg = <0xe0e00 0x200>;
  339. #sleep-cells = <2>;
  340. };
  341. /include/ "qoriq-clockgen1.dtsi"
  342. global-utilities@e1000 {
  343. compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
  344. };
  345. rcpm: global-utilities@e2000 {
  346. compatible = "fsl,qoriq-rcpm-1.0";
  347. reg = <0xe2000 0x1000>;
  348. #sleep-cells = <1>;
  349. };
  350. sfp: sfp@e8000 {
  351. compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
  352. reg = <0xe8000 0x1000>;
  353. };
  354. serdes: serdes@ea000 {
  355. compatible = "fsl,p4080-serdes";
  356. reg = <0xea000 0x1000>;
  357. };
  358. /include/ "qoriq-dma-0.dtsi"
  359. dma@100300 {
  360. fsl,iommu-parent = <&pamu0>;
  361. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  362. };
  363. /include/ "qoriq-dma-1.dtsi"
  364. dma@101300 {
  365. fsl,iommu-parent = <&pamu0>;
  366. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  367. };
  368. /include/ "qoriq-espi-0.dtsi"
  369. spi@110000 {
  370. fsl,espi-num-chipselects = <4>;
  371. };
  372. /include/ "qoriq-esdhc-0.dtsi"
  373. sdhc@114000 {
  374. compatible = "fsl,p4080-esdhc", "fsl,esdhc";
  375. fsl,iommu-parent = <&pamu1>;
  376. fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
  377. voltage-ranges = <3300 3300>;
  378. sdhci,auto-cmd12;
  379. };
  380. /include/ "qoriq-i2c-0.dtsi"
  381. /include/ "qoriq-i2c-1.dtsi"
  382. /include/ "qoriq-duart-0.dtsi"
  383. /include/ "qoriq-duart-1.dtsi"
  384. /include/ "qoriq-gpio-0.dtsi"
  385. /include/ "qoriq-usb2-mph-0.dtsi"
  386. usb@210000 {
  387. compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  388. fsl,iommu-parent = <&pamu1>;
  389. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  390. port0;
  391. };
  392. /include/ "qoriq-usb2-dr-0.dtsi"
  393. usb@211000 {
  394. compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  395. fsl,iommu-parent = <&pamu1>;
  396. fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
  397. };
  398. /include/ "qoriq-sec4.0-0.dtsi"
  399. crypto: crypto@300000 {
  400. fsl,iommu-parent = <&pamu1>;
  401. };
  402. /include/ "qoriq-qman1.dtsi"
  403. /include/ "qoriq-bman1.dtsi"
  404. /include/ "qoriq-fman-0.dtsi"
  405. /include/ "qoriq-fman-0-1g-0.dtsi"
  406. /include/ "qoriq-fman-0-1g-1.dtsi"
  407. /include/ "qoriq-fman-0-1g-2.dtsi"
  408. /include/ "qoriq-fman-0-1g-3.dtsi"
  409. /include/ "qoriq-fman-0-10g-0.dtsi"
  410. fman@400000 {
  411. enet0: ethernet@e0000 {
  412. };
  413. enet1: ethernet@e2000 {
  414. };
  415. enet2: ethernet@e4000 {
  416. };
  417. enet3: ethernet@e6000 {
  418. };
  419. enet4: ethernet@f0000 {
  420. };
  421. };
  422. /include/ "qoriq-fman-1.dtsi"
  423. /include/ "qoriq-fman-1-1g-0.dtsi"
  424. /include/ "qoriq-fman-1-1g-1.dtsi"
  425. /include/ "qoriq-fman-1-1g-2.dtsi"
  426. /include/ "qoriq-fman-1-1g-3.dtsi"
  427. /include/ "qoriq-fman-1-10g-0.dtsi"
  428. fman@500000 {
  429. enet5: ethernet@e0000 {
  430. };
  431. enet6: ethernet@e2000 {
  432. };
  433. enet7: ethernet@e4000 {
  434. };
  435. enet8: ethernet@e6000 {
  436. };
  437. enet9: ethernet@f0000 {
  438. };
  439. };
  440. };