p2020rdb.dts 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * P2020 RDB Device Tree Source
  4. *
  5. * Copyright 2009-2012 Freescale Semiconductor Inc.
  6. */
  7. /include/ "p2020si-pre.dtsi"
  8. / {
  9. model = "fsl,P2020RDB";
  10. compatible = "fsl,P2020RDB";
  11. aliases {
  12. ethernet0 = &enet0;
  13. ethernet1 = &enet1;
  14. ethernet2 = &enet2;
  15. serial0 = &serial0;
  16. serial1 = &serial1;
  17. pci0 = &pci0;
  18. pci1 = &pci1;
  19. };
  20. memory {
  21. device_type = "memory";
  22. };
  23. lbc: localbus@ffe05000 {
  24. reg = <0 0xffe05000 0 0x1000>;
  25. /* NOR and NAND Flashes */
  26. ranges = <0x0 0x0 0x0 0xef000000 0x01000000
  27. 0x1 0x0 0x0 0xffa00000 0x00040000
  28. 0x2 0x0 0x0 0xffb00000 0x00020000>;
  29. nor@0,0 {
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. compatible = "cfi-flash";
  33. reg = <0x0 0x0 0x1000000>;
  34. bank-width = <2>;
  35. device-width = <1>;
  36. partition@0 {
  37. /* This location must not be altered */
  38. /* 256KB for Vitesse 7385 Switch firmware */
  39. reg = <0x0 0x00040000>;
  40. label = "NOR (RO) Vitesse-7385 Firmware";
  41. read-only;
  42. };
  43. partition@40000 {
  44. /* 256KB for DTB Image */
  45. reg = <0x00040000 0x00040000>;
  46. label = "NOR (RO) DTB Image";
  47. read-only;
  48. };
  49. partition@80000 {
  50. /* 3.5 MB for Linux Kernel Image */
  51. reg = <0x00080000 0x00380000>;
  52. label = "NOR (RO) Linux Kernel Image";
  53. read-only;
  54. };
  55. partition@400000 {
  56. /* 11MB for JFFS2 based Root file System */
  57. reg = <0x00400000 0x00b00000>;
  58. label = "NOR (RW) JFFS2 Root File System";
  59. };
  60. partition@f00000 {
  61. /* This location must not be altered */
  62. /* 512KB for u-boot Bootloader Image */
  63. /* 512KB for u-boot Environment Variables */
  64. reg = <0x00f00000 0x00100000>;
  65. label = "NOR (RO) U-Boot Image";
  66. read-only;
  67. };
  68. };
  69. nand@1,0 {
  70. #address-cells = <1>;
  71. #size-cells = <1>;
  72. compatible = "fsl,p2020-fcm-nand",
  73. "fsl,elbc-fcm-nand";
  74. reg = <0x1 0x0 0x40000>;
  75. partition@0 {
  76. /* This location must not be altered */
  77. /* 1MB for u-boot Bootloader Image */
  78. reg = <0x0 0x00100000>;
  79. label = "NAND (RO) U-Boot Image";
  80. read-only;
  81. };
  82. partition@100000 {
  83. /* 1MB for DTB Image */
  84. reg = <0x00100000 0x00100000>;
  85. label = "NAND (RO) DTB Image";
  86. read-only;
  87. };
  88. partition@200000 {
  89. /* 4MB for Linux Kernel Image */
  90. reg = <0x00200000 0x00400000>;
  91. label = "NAND (RO) Linux Kernel Image";
  92. read-only;
  93. };
  94. partition@600000 {
  95. /* 4MB for Compressed Root file System Image */
  96. reg = <0x00600000 0x00400000>;
  97. label = "NAND (RO) Compressed RFS Image";
  98. read-only;
  99. };
  100. partition@a00000 {
  101. /* 7MB for JFFS2 based Root file System */
  102. reg = <0x00a00000 0x00700000>;
  103. label = "NAND (RW) JFFS2 Root File System";
  104. };
  105. partition@1100000 {
  106. /* 15MB for JFFS2 based Root file System */
  107. reg = <0x01100000 0x00f00000>;
  108. label = "NAND (RW) Writable User area";
  109. };
  110. };
  111. L2switch@2,0 {
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. compatible = "vitesse-7385";
  115. reg = <0x2 0x0 0x20000>;
  116. };
  117. };
  118. soc: soc@ffe00000 {
  119. ranges = <0x0 0x0 0xffe00000 0x100000>;
  120. i2c@3000 {
  121. rtc@68 {
  122. compatible = "dallas,ds1339";
  123. reg = <0x68>;
  124. };
  125. };
  126. spi@7000 {
  127. flash@0 {
  128. #address-cells = <1>;
  129. #size-cells = <1>;
  130. compatible = "spansion,s25sl12801", "jedec,spi-nor";
  131. reg = <0>;
  132. spi-max-frequency = <40000000>;
  133. partition@0 {
  134. /* 512KB for u-boot Bootloader Image */
  135. reg = <0x0 0x00080000>;
  136. label = "SPI (RO) U-Boot Image";
  137. read-only;
  138. };
  139. partition@80000 {
  140. /* 512KB for DTB Image */
  141. reg = <0x00080000 0x00080000>;
  142. label = "SPI (RO) DTB Image";
  143. read-only;
  144. };
  145. partition@100000 {
  146. /* 4MB for Linux Kernel Image */
  147. reg = <0x00100000 0x00400000>;
  148. label = "SPI (RO) Linux Kernel Image";
  149. read-only;
  150. };
  151. partition@500000 {
  152. /* 4MB for Compressed RFS Image */
  153. reg = <0x00500000 0x00400000>;
  154. label = "SPI (RO) Compressed RFS Image";
  155. read-only;
  156. };
  157. partition@900000 {
  158. /* 7MB for JFFS2 based RFS */
  159. reg = <0x00900000 0x00700000>;
  160. label = "SPI (RW) JFFS2 RFS";
  161. };
  162. };
  163. };
  164. usb@22000 {
  165. phy_type = "ulpi";
  166. dr_mode = "host";
  167. };
  168. mdio@24520 {
  169. phy0: ethernet-phy@0 {
  170. interrupts = <3 1 0 0>;
  171. reg = <0x0>;
  172. };
  173. phy1: ethernet-phy@1 {
  174. interrupts = <3 1 0 0>;
  175. reg = <0x1>;
  176. };
  177. tbi-phy@2 {
  178. device_type = "tbi-phy";
  179. reg = <0x2>;
  180. };
  181. };
  182. mdio@25520 {
  183. tbi0: tbi-phy@11 {
  184. reg = <0x11>;
  185. device_type = "tbi-phy";
  186. };
  187. };
  188. mdio@26520 {
  189. status = "disabled";
  190. };
  191. ptp_clock@24e00 {
  192. fsl,tclk-period = <5>;
  193. fsl,tmr-prsc = <200>;
  194. fsl,tmr-add = <0xCCCCCCCD>;
  195. fsl,tmr-fiper1 = <0x3B9AC9FB>;
  196. fsl,tmr-fiper2 = <0x0001869B>;
  197. fsl,max-adj = <249999999>;
  198. };
  199. enet0: ethernet@24000 {
  200. fixed-link = <1 1 1000 0 0>;
  201. phy-connection-type = "rgmii-id";
  202. };
  203. enet1: ethernet@25000 {
  204. tbi-handle = <&tbi0>;
  205. phy-handle = <&phy0>;
  206. phy-connection-type = "sgmii";
  207. };
  208. enet2: ethernet@26000 {
  209. phy-handle = <&phy1>;
  210. phy-connection-type = "rgmii-id";
  211. };
  212. };
  213. pci0: pcie@ffe08000 {
  214. reg = <0 0xffe08000 0 0x1000>;
  215. status = "disabled";
  216. };
  217. pci1: pcie@ffe09000 {
  218. reg = <0 0xffe09000 0 0x1000>;
  219. ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
  220. 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
  221. pcie@0 {
  222. ranges = <0x2000000 0x0 0xa0000000
  223. 0x2000000 0x0 0xa0000000
  224. 0x0 0x20000000
  225. 0x1000000 0x0 0x0
  226. 0x1000000 0x0 0x0
  227. 0x0 0x100000>;
  228. };
  229. };
  230. pci2: pcie@ffe0a000 {
  231. reg = <0 0xffe0a000 0 0x1000>;
  232. ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
  233. 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
  234. pcie@0 {
  235. ranges = <0x2000000 0x0 0x80000000
  236. 0x2000000 0x0 0x80000000
  237. 0x0 0x20000000
  238. 0x1000000 0x0 0x0
  239. 0x1000000 0x0 0x0
  240. 0x0 0x100000>;
  241. };
  242. };
  243. };
  244. /include/ "p2020si-post.dtsi"