mpc8641si-post.dtsi 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MPC8641 Silicon/SoC Device Tree Source (post include)
  4. *
  5. * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
  6. */
  7. &lbc {
  8. #address-cells = <2>;
  9. #size-cells = <1>;
  10. compatible = "fsl,mpc8641-localbus", "simple-bus";
  11. interrupts = <19 2 0 0>;
  12. };
  13. &soc {
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. device_type = "soc";
  17. compatible = "fsl,mpc8641-soc", "simple-bus";
  18. bus-frequency = <0>;
  19. mcm-law@0 {
  20. compatible = "fsl,mcm-law";
  21. reg = <0x0 0x1000>;
  22. fsl,num-laws = <10>;
  23. };
  24. mcm@1000 {
  25. compatible = "fsl,mpc8641-mcm", "fsl,mcm";
  26. reg = <0x1000 0x1000>;
  27. interrupts = <17 2 0 0>;
  28. };
  29. /include/ "pq3-i2c-0.dtsi"
  30. /include/ "pq3-i2c-1.dtsi"
  31. /include/ "pq3-duart-0.dtsi"
  32. serial@4600 {
  33. interrupts = <28 2 0 0>;
  34. };
  35. /include/ "pq3-dma-0.dtsi"
  36. dma@21300 {
  37. compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
  38. };
  39. dma-channel@0 {
  40. compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
  41. };
  42. dma-channel@80 {
  43. compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
  44. };
  45. dma-channel@100 {
  46. compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
  47. };
  48. dma-channel@180 {
  49. compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
  50. };
  51. /include/ "pq3-etsec1-0.dtsi"
  52. ethernet@24000 {
  53. model = "TSEC";
  54. };
  55. /include/ "pq3-etsec1-1.dtsi"
  56. ethernet@25000 {
  57. model = "TSEC";
  58. };
  59. /include/ "pq3-etsec1-2.dtsi"
  60. ethernet@26000 {
  61. model = "TSEC";
  62. };
  63. /include/ "pq3-etsec1-3.dtsi"
  64. ethernet@27000 {
  65. model = "TSEC";
  66. };
  67. /include/ "qoriq-mpic.dtsi"
  68. msi@41600 {
  69. compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
  70. };
  71. msi@41800 {
  72. compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
  73. };
  74. msi@41a00 {
  75. compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
  76. };
  77. global-utilities@e0000 {
  78. compatible = "fsl,mpc8641-guts";
  79. reg = <0xe0000 0x1000>;
  80. fsl,has-rstcr;
  81. };
  82. };
  83. &pci0 {
  84. compatible = "fsl,mpc8641-pcie";
  85. device_type = "pci";
  86. #interrupt-cells = <1>;
  87. #size-cells = <2>;
  88. #address-cells = <3>;
  89. bus-range = <0x0 0xff>;
  90. clock-frequency = <100000000>;
  91. interrupts = <24 2 0 0>;
  92. pcie@0 {
  93. reg = <0 0 0 0 0>;
  94. #interrupt-cells = <1>;
  95. #size-cells = <2>;
  96. #address-cells = <3>;
  97. device_type = "pci";
  98. interrupts = <24 2 0 0>;
  99. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  100. interrupt-map = <
  101. 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  102. 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  103. 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  104. 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  105. >;
  106. };
  107. };
  108. &pci1 {
  109. compatible = "fsl,mpc8641-pcie";
  110. device_type = "pci";
  111. #interrupt-cells = <1>;
  112. #size-cells = <2>;
  113. #address-cells = <3>;
  114. bus-range = <0x0 0xff>;
  115. clock-frequency = <100000000>;
  116. interrupts = <25 2 0 0>;
  117. pcie@0 {
  118. reg = <0 0 0 0 0>;
  119. #interrupt-cells = <1>;
  120. #size-cells = <2>;
  121. #address-cells = <3>;
  122. device_type = "pci";
  123. interrupts = <25 2 0 0>;
  124. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  125. interrupt-map = <
  126. 0x0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
  127. 0x0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
  128. 0x0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
  129. 0x0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
  130. >;
  131. };
  132. };