c293si-post.dtsi 4.6 KB

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  1. /*
  2. * C293 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2012 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &ifc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. compatible = "fsl,ifc", "simple-bus";
  38. interrupts = <19 2 0 0>;
  39. };
  40. /* controller at 0xa000 */
  41. &pci0 {
  42. compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0 255>;
  47. clock-frequency = <33333333>;
  48. interrupts = <16 2 0 0>;
  49. pcie@0 {
  50. reg = <0 0 0 0 0>;
  51. #interrupt-cells = <1>;
  52. #size-cells = <2>;
  53. #address-cells = <3>;
  54. device_type = "pci";
  55. interrupts = <16 2 0 0>;
  56. interrupt-map-mask = <0xf800 0 0 7>;
  57. interrupt-map = <
  58. /* IDSEL 0x0 */
  59. 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  60. 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  61. 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  62. 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  63. >;
  64. };
  65. };
  66. &soc {
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. device_type = "soc";
  70. compatible = "simple-bus";
  71. bus-frequency = <0>; // Filled out by uboot.
  72. ecm-law@0 {
  73. compatible = "fsl,ecm-law";
  74. reg = <0x0 0x1000>;
  75. fsl,num-laws = <12>;
  76. };
  77. ecm@1000 {
  78. compatible = "fsl,c293-ecm", "fsl,ecm";
  79. reg = <0x1000 0x1000>;
  80. interrupts = <16 2 0 0>;
  81. };
  82. memory-controller@2000 {
  83. compatible = "fsl,c293-memory-controller";
  84. reg = <0x2000 0x1000>;
  85. interrupts = <16 2 0 0>;
  86. };
  87. /include/ "pq3-i2c-0.dtsi"
  88. /include/ "pq3-i2c-1.dtsi"
  89. /include/ "pq3-duart-0.dtsi"
  90. /include/ "pq3-espi-0.dtsi"
  91. spi0: spi@7000 {
  92. fsl,espi-num-chipselects = <1>;
  93. };
  94. /include/ "pq3-gpio-0.dtsi"
  95. L2: l2-cache-controller@20000 {
  96. compatible = "fsl,c293-l2-cache-controller";
  97. reg = <0x20000 0x1000>;
  98. cache-line-size = <32>; // 32 bytes
  99. cache-size = <0x80000>; // L2,512K
  100. interrupts = <16 2 0 0>;
  101. };
  102. /include/ "pq3-dma-0.dtsi"
  103. /include/ "pq3-esdhc-0.dtsi"
  104. sdhc@2e000 {
  105. compatible = "fsl,c293-esdhc", "fsl,esdhc";
  106. sdhci,auto-cmd12;
  107. };
  108. crypto@80000 {
  109. /include/ "qoriq-sec6.0-0.dtsi"
  110. };
  111. crypto@80000 {
  112. reg = <0x80000 0x20000>;
  113. ranges = <0x0 0x80000 0x20000>;
  114. jr@1000{
  115. interrupts = <45 2 0 0>;
  116. };
  117. jr@2000{
  118. interrupts = <57 2 0 0>;
  119. };
  120. };
  121. crypto@a0000 {
  122. /include/ "qoriq-sec6.0-0.dtsi"
  123. };
  124. crypto@a0000 {
  125. reg = <0xa0000 0x20000>;
  126. ranges = <0x0 0xa0000 0x20000>;
  127. jr@1000{
  128. interrupts = <49 2 0 0>;
  129. };
  130. jr@2000{
  131. interrupts = <50 2 0 0>;
  132. };
  133. };
  134. crypto@c0000 {
  135. /include/ "qoriq-sec6.0-0.dtsi"
  136. };
  137. crypto@c0000 {
  138. reg = <0xc0000 0x20000>;
  139. ranges = <0x0 0xc0000 0x20000>;
  140. jr@1000{
  141. interrupts = <55 2 0 0>;
  142. };
  143. jr@2000{
  144. interrupts = <56 2 0 0>;
  145. };
  146. };
  147. /include/ "pq3-mpic.dtsi"
  148. /include/ "pq3-mpic-timer-B.dtsi"
  149. /include/ "pq3-etsec2-0.dtsi"
  150. enet0: ethernet@b0000 {
  151. queue-group@b0000 {
  152. reg = <0x10000 0x1000>;
  153. };
  154. };
  155. /include/ "pq3-etsec2-1.dtsi"
  156. enet1: ethernet@b1000 {
  157. queue-group@b1000 {
  158. reg = <0x11000 0x1000>;
  159. };
  160. };
  161. global-utilities@e0000 {
  162. compatible = "fsl,c293-guts";
  163. reg = <0xe0000 0x1000>;
  164. fsl,has-rstcr;
  165. };
  166. };