or1ksim.dts 1.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. / {
  4. compatible = "opencores,or1ksim";
  5. #address-cells = <1>;
  6. #size-cells = <1>;
  7. interrupt-parent = <&pic>;
  8. aliases {
  9. uart0 = &serial0;
  10. };
  11. chosen {
  12. bootargs = "earlycon";
  13. stdout-path = "uart0:115200";
  14. };
  15. memory@0 {
  16. device_type = "memory";
  17. reg = <0x00000000 0x02000000>;
  18. };
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. cpu@0 {
  23. compatible = "opencores,or1200-rtlsvn481";
  24. reg = <0>;
  25. clock-frequency = <20000000>;
  26. };
  27. };
  28. /*
  29. * OR1K PIC is built into CPU and accessed via special purpose
  30. * registers. It is not addressable and, hence, has no 'reg'
  31. * property.
  32. */
  33. pic: pic {
  34. compatible = "opencores,or1k-pic";
  35. #interrupt-cells = <1>;
  36. interrupt-controller;
  37. };
  38. serial0: serial@90000000 {
  39. compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
  40. reg = <0x90000000 0x100>;
  41. interrupts = <2>;
  42. clock-frequency = <20000000>;
  43. };
  44. enet0: ethoc@92000000 {
  45. compatible = "opencores,ethoc";
  46. reg = <0x92000000 0x800>;
  47. interrupts = <4>;
  48. big-endian;
  49. };
  50. };