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android_kernel_...
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arch
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mips
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include
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asm
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sgi
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pi1.h

pi1.h 1.9 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /*
    3. 

  3.  * pi1.h: Definitions for SGI PI1 parallel port
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _SGI_PI1_H
    7. 

  7. #define _SGI_PI1_H
    8. 

  8. 

  9. struct pi1_regs {
    10. 

  10. 	u8 _data[3];
    11. 

  11. 	volatile u8 data;
    12. 

  12. 	u8 _ctrl[3];
    13. 

  13. 	volatile u8 ctrl;
    14. 

  14. #define PI1_CTRL_STROBE_N	0x01
    15. 

  15. #define PI1_CTRL_AFD_N		0x02
    16. 

  16. #define PI1_CTRL_INIT_N		0x04
    17. 

  17. #define PI1_CTRL_SLIN_N		0x08
    18. 

  18. #define PI1_CTRL_IRQ_ENA	0x10
    19. 

  19. #define PI1_CTRL_DIR		0x20
    20. 

  20. #define PI1_CTRL_SEL		0x40
    21. 

  21. 	u8 _status[3];
    22. 

  22. 	volatile u8 status;
    23. 

  23. #define PI1_STAT_DEVID		0x03	/* bits 0-1 */
    24. 

  24. #define PI1_STAT_NOINK		0x04	/* SGI MODE only */
    25. 

  25. #define PI1_STAT_ERROR		0x08
    26. 

  26. #define PI1_STAT_ONLINE		0x10
    27. 

  27. #define PI1_STAT_PE		0x20
    28. 

  28. #define PI1_STAT_ACK		0x40
    29. 

  29. #define PI1_STAT_BUSY		0x80
    30. 

  30. 	u8 _dmactrl[3];
    31. 

  31. 	volatile u8 dmactrl;
    32. 

  32. #define PI1_DMACTRL_FIFO_EMPTY	0x01	/* fifo empty R/O */
    33. 

  33. #define PI1_DMACTRL_ABORT	0x02	/* reset DMA and internal fifo W/O */
    34. 

  34. #define PI1_DMACTRL_STDMODE	0x00	/* bits 2-3 */
    35. 

  35. #define PI1_DMACTRL_SGIMODE	0x04	/* bits 2-3 */
    36. 

  36. #define PI1_DMACTRL_RICOHMODE	0x08	/* bits 2-3 */
    37. 

  37. #define PI1_DMACTRL_HPMODE	0x0c	/* bits 2-3 */
    38. 

  38. #define PI1_DMACTRL_BLKMODE	0x10	/* block mode */
    39. 

  39. #define PI1_DMACTRL_FIFO_CLEAR	0x20	/* clear fifo W/O */
    40. 

  40. #define PI1_DMACTRL_READ	0x40	/* read */
    41. 

  41. #define PI1_DMACTRL_RUN		0x80	/* pedal to the metal */
    42. 

  42. 	u8 _intstat[3];
    43. 

  43. 	volatile u8 intstat;
    44. 

  44. #define PI1_INTSTAT_ACK		0x04
    45. 

  45. #define PI1_INTSTAT_FEMPTY	0x08
    46. 

  46. #define PI1_INTSTAT_NOINK	0x10
    47. 

  47. #define PI1_INTSTAT_ONLINE	0x20
    48. 

  48. #define PI1_INTSTAT_ERR		0x40
    49. 

  49. #define PI1_INTSTAT_PE		0x80
    50. 

  50. 	u8 _intmask[3];
    51. 

  51. 	volatile u8 intmask;		/* enabled low, reset high*/
    52. 

  52. #define PI1_INTMASK_ACK		0x04
    53. 

  53. #define PI1_INTMASK_FIFO_EMPTY	0x08
    54. 

  54. #define PI1_INTMASK_NOINK	0x10
    55. 

  55. #define PI1_INTMASK_ONLINE	0x20
    56. 

  56. #define PI1_INTMASK_ERR		0x40
    57. 

  57. #define PI1_INTMASK_PE		0x80
    58. 

  58. 	u8 _timer1[3];
    59. 

  59. 	volatile u8 timer1;
    60. 

  60. #define PI1_TIME1		0x27
    61. 

  61. 	u8 _timer2[3];
    62. 

  62. 	volatile u8 timer2;
    63. 

  63. #define PI1_TIME2		0x13
    64. 

  64. 	u8 _timer3[3];
    65. 

  65. 	volatile u8 timer3;
    66. 

  66. #define PI1_TIME3		0x10
    67. 

  67. 	u8 _timer4[3];
    68. 

  68. 	volatile u8 timer4;
    69. 

  69. #define PI1_TIME4		0x00
    70. 

  70. };
    71. 

  71. 

  72. #endif
    73.