cvmx-interrupt-decodes.c 14 KB

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  1. /***********************license start***************
  2. * Author: Cavium Networks
  3. *
  4. * Contact: [email protected]
  5. * This file is part of the OCTEON SDK
  6. *
  7. * Copyright (c) 2003-2009 Cavium Networks
  8. *
  9. * This file is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License, Version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful, but
  14. * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16. * NONINFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this file; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22. * or visit http://www.gnu.org/licenses/.
  23. *
  24. * This file may also be available under a different license from Cavium.
  25. * Contact Cavium Networks for more information
  26. ***********************license end**************************************/
  27. /*
  28. *
  29. * Automatically generated functions useful for enabling
  30. * and decoding RSL_INT_BLOCKS interrupts.
  31. *
  32. */
  33. #include <asm/octeon/octeon.h>
  34. #include <asm/octeon/cvmx-gmxx-defs.h>
  35. #include <asm/octeon/cvmx-pcsx-defs.h>
  36. #include <asm/octeon/cvmx-pcsxx-defs.h>
  37. #include <asm/octeon/cvmx-spxx-defs.h>
  38. #include <asm/octeon/cvmx-stxx-defs.h>
  39. #ifndef PRINT_ERROR
  40. #define PRINT_ERROR(format, ...)
  41. #endif
  42. /**
  43. * __cvmx_interrupt_gmxx_rxx_int_en_enable - enable all interrupt bits in cvmx_gmxx_rxx_int_en_t
  44. * @index: interrupt register offset
  45. * @block: interrupt register block_id
  46. */
  47. void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
  48. {
  49. union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
  50. cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block),
  51. cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));
  52. gmx_rx_int_en.u64 = 0;
  53. if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
  54. /* Skipping gmx_rx_int_en.s.reserved_29_63 */
  55. gmx_rx_int_en.s.hg2cc = 1;
  56. gmx_rx_int_en.s.hg2fld = 1;
  57. gmx_rx_int_en.s.undat = 1;
  58. gmx_rx_int_en.s.uneop = 1;
  59. gmx_rx_int_en.s.unsop = 1;
  60. gmx_rx_int_en.s.bad_term = 1;
  61. gmx_rx_int_en.s.bad_seq = 1;
  62. gmx_rx_int_en.s.rem_fault = 1;
  63. gmx_rx_int_en.s.loc_fault = 1;
  64. gmx_rx_int_en.s.pause_drp = 1;
  65. /* Skipping gmx_rx_int_en.s.reserved_16_18 */
  66. /*gmx_rx_int_en.s.ifgerr = 1; */
  67. /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
  68. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  69. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  70. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  71. gmx_rx_int_en.s.ovrerr = 1;
  72. /* Skipping gmx_rx_int_en.s.reserved_9_9 */
  73. gmx_rx_int_en.s.skperr = 1;
  74. gmx_rx_int_en.s.rcverr = 1;
  75. /* Skipping gmx_rx_int_en.s.reserved_5_6 */
  76. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  77. gmx_rx_int_en.s.jabber = 1;
  78. /* Skipping gmx_rx_int_en.s.reserved_2_2 */
  79. gmx_rx_int_en.s.carext = 1;
  80. /* Skipping gmx_rx_int_en.s.reserved_0_0 */
  81. }
  82. if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
  83. /* Skipping gmx_rx_int_en.s.reserved_19_63 */
  84. /*gmx_rx_int_en.s.phy_dupx = 1; */
  85. /*gmx_rx_int_en.s.phy_spd = 1; */
  86. /*gmx_rx_int_en.s.phy_link = 1; */
  87. /*gmx_rx_int_en.s.ifgerr = 1; */
  88. /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
  89. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  90. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  91. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  92. gmx_rx_int_en.s.ovrerr = 1;
  93. gmx_rx_int_en.s.niberr = 1;
  94. gmx_rx_int_en.s.skperr = 1;
  95. gmx_rx_int_en.s.rcverr = 1;
  96. /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
  97. gmx_rx_int_en.s.alnerr = 1;
  98. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  99. gmx_rx_int_en.s.jabber = 1;
  100. gmx_rx_int_en.s.maxerr = 1;
  101. gmx_rx_int_en.s.carext = 1;
  102. gmx_rx_int_en.s.minerr = 1;
  103. }
  104. if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
  105. /* Skipping gmx_rx_int_en.s.reserved_20_63 */
  106. gmx_rx_int_en.s.pause_drp = 1;
  107. /*gmx_rx_int_en.s.phy_dupx = 1; */
  108. /*gmx_rx_int_en.s.phy_spd = 1; */
  109. /*gmx_rx_int_en.s.phy_link = 1; */
  110. /*gmx_rx_int_en.s.ifgerr = 1; */
  111. /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
  112. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  113. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  114. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  115. gmx_rx_int_en.s.ovrerr = 1;
  116. gmx_rx_int_en.s.niberr = 1;
  117. gmx_rx_int_en.s.skperr = 1;
  118. gmx_rx_int_en.s.rcverr = 1;
  119. /* Skipping gmx_rx_int_en.s.reserved_6_6 */
  120. gmx_rx_int_en.s.alnerr = 1;
  121. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  122. gmx_rx_int_en.s.jabber = 1;
  123. /* Skipping gmx_rx_int_en.s.reserved_2_2 */
  124. gmx_rx_int_en.s.carext = 1;
  125. /* Skipping gmx_rx_int_en.s.reserved_0_0 */
  126. }
  127. if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
  128. /* Skipping gmx_rx_int_en.s.reserved_19_63 */
  129. /*gmx_rx_int_en.s.phy_dupx = 1; */
  130. /*gmx_rx_int_en.s.phy_spd = 1; */
  131. /*gmx_rx_int_en.s.phy_link = 1; */
  132. /*gmx_rx_int_en.s.ifgerr = 1; */
  133. /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
  134. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  135. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  136. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  137. gmx_rx_int_en.s.ovrerr = 1;
  138. gmx_rx_int_en.s.niberr = 1;
  139. gmx_rx_int_en.s.skperr = 1;
  140. gmx_rx_int_en.s.rcverr = 1;
  141. /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
  142. gmx_rx_int_en.s.alnerr = 1;
  143. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  144. gmx_rx_int_en.s.jabber = 1;
  145. gmx_rx_int_en.s.maxerr = 1;
  146. gmx_rx_int_en.s.carext = 1;
  147. gmx_rx_int_en.s.minerr = 1;
  148. }
  149. if (OCTEON_IS_MODEL(OCTEON_CN31XX)) {
  150. /* Skipping gmx_rx_int_en.s.reserved_19_63 */
  151. /*gmx_rx_int_en.s.phy_dupx = 1; */
  152. /*gmx_rx_int_en.s.phy_spd = 1; */
  153. /*gmx_rx_int_en.s.phy_link = 1; */
  154. /*gmx_rx_int_en.s.ifgerr = 1; */
  155. /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
  156. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  157. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  158. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  159. gmx_rx_int_en.s.ovrerr = 1;
  160. gmx_rx_int_en.s.niberr = 1;
  161. gmx_rx_int_en.s.skperr = 1;
  162. gmx_rx_int_en.s.rcverr = 1;
  163. /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
  164. gmx_rx_int_en.s.alnerr = 1;
  165. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  166. gmx_rx_int_en.s.jabber = 1;
  167. gmx_rx_int_en.s.maxerr = 1;
  168. gmx_rx_int_en.s.carext = 1;
  169. gmx_rx_int_en.s.minerr = 1;
  170. }
  171. if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  172. /* Skipping gmx_rx_int_en.s.reserved_20_63 */
  173. gmx_rx_int_en.s.pause_drp = 1;
  174. /*gmx_rx_int_en.s.phy_dupx = 1; */
  175. /*gmx_rx_int_en.s.phy_spd = 1; */
  176. /*gmx_rx_int_en.s.phy_link = 1; */
  177. /*gmx_rx_int_en.s.ifgerr = 1; */
  178. /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
  179. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  180. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  181. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  182. gmx_rx_int_en.s.ovrerr = 1;
  183. gmx_rx_int_en.s.niberr = 1;
  184. gmx_rx_int_en.s.skperr = 1;
  185. gmx_rx_int_en.s.rcverr = 1;
  186. /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
  187. gmx_rx_int_en.s.alnerr = 1;
  188. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  189. gmx_rx_int_en.s.jabber = 1;
  190. gmx_rx_int_en.s.maxerr = 1;
  191. gmx_rx_int_en.s.carext = 1;
  192. gmx_rx_int_en.s.minerr = 1;
  193. }
  194. if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
  195. /* Skipping gmx_rx_int_en.s.reserved_29_63 */
  196. gmx_rx_int_en.s.hg2cc = 1;
  197. gmx_rx_int_en.s.hg2fld = 1;
  198. gmx_rx_int_en.s.undat = 1;
  199. gmx_rx_int_en.s.uneop = 1;
  200. gmx_rx_int_en.s.unsop = 1;
  201. gmx_rx_int_en.s.bad_term = 1;
  202. gmx_rx_int_en.s.bad_seq = 0;
  203. gmx_rx_int_en.s.rem_fault = 1;
  204. gmx_rx_int_en.s.loc_fault = 0;
  205. gmx_rx_int_en.s.pause_drp = 1;
  206. /* Skipping gmx_rx_int_en.s.reserved_16_18 */
  207. /*gmx_rx_int_en.s.ifgerr = 1; */
  208. /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
  209. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  210. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  211. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  212. gmx_rx_int_en.s.ovrerr = 1;
  213. /* Skipping gmx_rx_int_en.s.reserved_9_9 */
  214. gmx_rx_int_en.s.skperr = 1;
  215. gmx_rx_int_en.s.rcverr = 1;
  216. /* Skipping gmx_rx_int_en.s.reserved_5_6 */
  217. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  218. gmx_rx_int_en.s.jabber = 1;
  219. /* Skipping gmx_rx_int_en.s.reserved_2_2 */
  220. gmx_rx_int_en.s.carext = 1;
  221. /* Skipping gmx_rx_int_en.s.reserved_0_0 */
  222. }
  223. cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64);
  224. }
  225. /**
  226. * __cvmx_interrupt_pcsx_intx_en_reg_enable - enable all interrupt bits in cvmx_pcsx_intx_en_reg_t
  227. * @index: interrupt register offset
  228. * @block: interrupt register block_id
  229. */
  230. void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block)
  231. {
  232. union cvmx_pcsx_intx_en_reg pcs_int_en_reg;
  233. cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block),
  234. cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block)));
  235. pcs_int_en_reg.u64 = 0;
  236. if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
  237. /* Skipping pcs_int_en_reg.s.reserved_12_63 */
  238. /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
  239. pcs_int_en_reg.s.sync_bad_en = 1;
  240. pcs_int_en_reg.s.an_bad_en = 1;
  241. pcs_int_en_reg.s.rxlock_en = 1;
  242. pcs_int_en_reg.s.rxbad_en = 1;
  243. /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
  244. pcs_int_en_reg.s.txbad_en = 1;
  245. pcs_int_en_reg.s.txfifo_en = 1;
  246. pcs_int_en_reg.s.txfifu_en = 1;
  247. pcs_int_en_reg.s.an_err_en = 1;
  248. /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
  249. /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
  250. }
  251. if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
  252. /* Skipping pcs_int_en_reg.s.reserved_12_63 */
  253. /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
  254. pcs_int_en_reg.s.sync_bad_en = 1;
  255. pcs_int_en_reg.s.an_bad_en = 1;
  256. pcs_int_en_reg.s.rxlock_en = 1;
  257. pcs_int_en_reg.s.rxbad_en = 1;
  258. /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
  259. pcs_int_en_reg.s.txbad_en = 1;
  260. pcs_int_en_reg.s.txfifo_en = 1;
  261. pcs_int_en_reg.s.txfifu_en = 1;
  262. pcs_int_en_reg.s.an_err_en = 1;
  263. /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
  264. /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
  265. }
  266. cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);
  267. }
  268. /**
  269. * __cvmx_interrupt_pcsxx_int_en_reg_enable - enable all interrupt bits in cvmx_pcsxx_int_en_reg_t
  270. * @index: interrupt register block_id
  271. */
  272. void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index)
  273. {
  274. union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
  275. cvmx_write_csr(CVMX_PCSXX_INT_REG(index),
  276. cvmx_read_csr(CVMX_PCSXX_INT_REG(index)));
  277. pcsx_int_en_reg.u64 = 0;
  278. if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
  279. /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
  280. pcsx_int_en_reg.s.algnlos_en = 1;
  281. pcsx_int_en_reg.s.synlos_en = 1;
  282. pcsx_int_en_reg.s.bitlckls_en = 1;
  283. pcsx_int_en_reg.s.rxsynbad_en = 1;
  284. pcsx_int_en_reg.s.rxbad_en = 1;
  285. pcsx_int_en_reg.s.txflt_en = 1;
  286. }
  287. if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
  288. /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
  289. pcsx_int_en_reg.s.algnlos_en = 1;
  290. pcsx_int_en_reg.s.synlos_en = 1;
  291. pcsx_int_en_reg.s.bitlckls_en = 0; /* Happens if XAUI module is not installed */
  292. pcsx_int_en_reg.s.rxsynbad_en = 1;
  293. pcsx_int_en_reg.s.rxbad_en = 1;
  294. pcsx_int_en_reg.s.txflt_en = 1;
  295. }
  296. cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);
  297. }
  298. /**
  299. * __cvmx_interrupt_spxx_int_msk_enable - enable all interrupt bits in cvmx_spxx_int_msk_t
  300. * @index: interrupt register block_id
  301. */
  302. void __cvmx_interrupt_spxx_int_msk_enable(int index)
  303. {
  304. union cvmx_spxx_int_msk spx_int_msk;
  305. cvmx_write_csr(CVMX_SPXX_INT_REG(index),
  306. cvmx_read_csr(CVMX_SPXX_INT_REG(index)));
  307. spx_int_msk.u64 = 0;
  308. if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
  309. /* Skipping spx_int_msk.s.reserved_12_63 */
  310. spx_int_msk.s.calerr = 1;
  311. spx_int_msk.s.syncerr = 1;
  312. spx_int_msk.s.diperr = 1;
  313. spx_int_msk.s.tpaovr = 1;
  314. spx_int_msk.s.rsverr = 1;
  315. spx_int_msk.s.drwnng = 1;
  316. spx_int_msk.s.clserr = 1;
  317. spx_int_msk.s.spiovr = 1;
  318. /* Skipping spx_int_msk.s.reserved_2_3 */
  319. spx_int_msk.s.abnorm = 1;
  320. spx_int_msk.s.prtnxa = 1;
  321. }
  322. if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  323. /* Skipping spx_int_msk.s.reserved_12_63 */
  324. spx_int_msk.s.calerr = 1;
  325. spx_int_msk.s.syncerr = 1;
  326. spx_int_msk.s.diperr = 1;
  327. spx_int_msk.s.tpaovr = 1;
  328. spx_int_msk.s.rsverr = 1;
  329. spx_int_msk.s.drwnng = 1;
  330. spx_int_msk.s.clserr = 1;
  331. spx_int_msk.s.spiovr = 1;
  332. /* Skipping spx_int_msk.s.reserved_2_3 */
  333. spx_int_msk.s.abnorm = 1;
  334. spx_int_msk.s.prtnxa = 1;
  335. }
  336. cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);
  337. }
  338. /**
  339. * __cvmx_interrupt_stxx_int_msk_enable - enable all interrupt bits in cvmx_stxx_int_msk_t
  340. * @index: interrupt register block_id
  341. */
  342. void __cvmx_interrupt_stxx_int_msk_enable(int index)
  343. {
  344. union cvmx_stxx_int_msk stx_int_msk;
  345. cvmx_write_csr(CVMX_STXX_INT_REG(index),
  346. cvmx_read_csr(CVMX_STXX_INT_REG(index)));
  347. stx_int_msk.u64 = 0;
  348. if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
  349. /* Skipping stx_int_msk.s.reserved_8_63 */
  350. stx_int_msk.s.frmerr = 1;
  351. stx_int_msk.s.unxfrm = 1;
  352. stx_int_msk.s.nosync = 1;
  353. stx_int_msk.s.diperr = 1;
  354. stx_int_msk.s.datovr = 1;
  355. stx_int_msk.s.ovrbst = 1;
  356. stx_int_msk.s.calpar1 = 1;
  357. stx_int_msk.s.calpar0 = 1;
  358. }
  359. if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  360. /* Skipping stx_int_msk.s.reserved_8_63 */
  361. stx_int_msk.s.frmerr = 1;
  362. stx_int_msk.s.unxfrm = 1;
  363. stx_int_msk.s.nosync = 1;
  364. stx_int_msk.s.diperr = 1;
  365. stx_int_msk.s.datovr = 1;
  366. stx_int_msk.s.ovrbst = 1;
  367. stx_int_msk.s.calpar1 = 1;
  368. stx_int_msk.s.calpar0 = 1;
  369. }
  370. cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);
  371. }