malta.dts 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/interrupt-controller/irq.h>
  4. #include <dt-bindings/interrupt-controller/mips-gic.h>
  5. /memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */
  6. /memreserve/ 0x00001000 0x000ef000; /* YAMON */
  7. /memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
  8. / {
  9. #address-cells = <1>;
  10. #size-cells = <1>;
  11. compatible = "mti,malta";
  12. cpu_intc: interrupt-controller {
  13. compatible = "mti,cpu-interrupt-controller";
  14. interrupt-controller;
  15. #interrupt-cells = <1>;
  16. };
  17. gic: interrupt-controller@1bdc0000 {
  18. compatible = "mti,gic";
  19. reg = <0x1bdc0000 0x20000>;
  20. interrupt-controller;
  21. #interrupt-cells = <3>;
  22. /*
  23. * Declare the interrupt-parent even though the mti,gic
  24. * binding doesn't require it, such that the kernel can
  25. * figure out that cpu_intc is the root interrupt
  26. * controller & should be probed first.
  27. */
  28. interrupt-parent = <&cpu_intc>;
  29. timer {
  30. compatible = "mti,gic-timer";
  31. interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
  32. };
  33. };
  34. i8259: interrupt-controller@20 {
  35. compatible = "intel,i8259";
  36. interrupt-controller;
  37. #interrupt-cells = <1>;
  38. interrupt-parent = <&gic>;
  39. interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
  40. };
  41. flash@1e000000 {
  42. compatible = "intel,dt28f160", "cfi-flash";
  43. reg = <0x1e000000 0x400000>;
  44. bank-width = <4>;
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. partitions {
  48. compatible = "fixed-partitions";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. yamon@0 {
  52. label = "YAMON";
  53. reg = <0x0 0x100000>;
  54. read-only;
  55. };
  56. user-fs@100000 {
  57. label = "User FS";
  58. reg = <0x100000 0x2e0000>;
  59. };
  60. board-config@3e0000 {
  61. label = "Board Config";
  62. reg = <0x3e0000 0x20000>;
  63. read-only;
  64. };
  65. };
  66. };
  67. fpga_regs: system-controller@1f000000 {
  68. compatible = "mti,malta-fpga", "syscon", "simple-mfd";
  69. reg = <0x1f000000 0x1000>;
  70. native-endian;
  71. lcd@410 {
  72. compatible = "mti,malta-lcd";
  73. offset = <0x410>;
  74. };
  75. reboot {
  76. compatible = "syscon-reboot";
  77. regmap = <&fpga_regs>;
  78. offset = <0x500>;
  79. mask = <0x42>;
  80. };
  81. };
  82. isa {
  83. compatible = "isa";
  84. #address-cells = <2>;
  85. #size-cells = <1>;
  86. ranges = <1 0 0 0x1000>;
  87. rtc@70 {
  88. compatible = "motorola,mc146818";
  89. reg = <1 0x70 0x8>;
  90. interrupt-parent = <&i8259>;
  91. interrupts = <8>;
  92. };
  93. };
  94. };