serval.dtsi 2.9 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Microsemi Corporation
  4. */
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. compatible = "mscc,serval";
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. cpu@0 {
  13. compatible = "mips,mips24KEc";
  14. device_type = "cpu";
  15. clocks = <&cpu_clk>;
  16. reg = <0>;
  17. };
  18. };
  19. aliases {
  20. serial0 = &uart0;
  21. gpio0 = &gpio;
  22. };
  23. cpuintc: interrupt-controller {
  24. #address-cells = <0>;
  25. #interrupt-cells = <1>;
  26. interrupt-controller;
  27. compatible = "mti,cpu-interrupt-controller";
  28. };
  29. cpu_clk: cpu-clock {
  30. compatible = "fixed-clock";
  31. #clock-cells = <0>;
  32. clock-frequency = <416666666>;
  33. };
  34. ahb_clk: ahb-clk {
  35. compatible = "fixed-factor-clock";
  36. #clock-cells = <0>;
  37. clocks = <&cpu_clk>;
  38. clock-div = <2>;
  39. clock-mult = <1>;
  40. };
  41. ahb: ahb {
  42. compatible = "simple-bus";
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. ranges;
  46. interrupt-parent = <&intc>;
  47. cpu_ctrl: syscon@70000000 {
  48. compatible = "mscc,ocelot-cpu-syscon", "syscon";
  49. reg = <0x70000000 0x2c>;
  50. };
  51. intc: interrupt-controller@70000070 {
  52. compatible = "mscc,serval-icpu-intr";
  53. reg = <0x70000070 0x70>;
  54. #interrupt-cells = <1>;
  55. interrupt-controller;
  56. interrupt-parent = <&cpuintc>;
  57. interrupts = <2>;
  58. };
  59. uart0: serial@70100000 {
  60. pinctrl-0 = <&uart_pins>;
  61. pinctrl-names = "default";
  62. compatible = "ns16550a";
  63. reg = <0x70100000 0x20>;
  64. interrupts = <6>;
  65. clocks = <&ahb_clk>;
  66. reg-io-width = <4>;
  67. reg-shift = <2>;
  68. status = "disabled";
  69. };
  70. uart2: serial@70100800 {
  71. pinctrl-0 = <&uart2_pins>;
  72. pinctrl-names = "default";
  73. compatible = "ns16550a";
  74. reg = <0x70100800 0x20>;
  75. interrupts = <7>;
  76. clocks = <&ahb_clk>;
  77. reg-io-width = <4>;
  78. reg-shift = <2>;
  79. status = "disabled";
  80. };
  81. gpio: pinctrl@71070034 {
  82. compatible = "mscc,serval-pinctrl";
  83. reg = <0x71070034 0x28>;
  84. gpio-controller;
  85. #gpio-cells = <2>;
  86. gpio-ranges = <&gpio 0 0 22>;
  87. sgpio_pins: sgpio-pins {
  88. pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
  89. function = "sg0";
  90. };
  91. i2c_pins: i2c-pins {
  92. pins = "GPIO_6", "GPIO_7";
  93. function = "twi";
  94. };
  95. uart_pins: uart-pins {
  96. pins = "GPIO_26", "GPIO_27";
  97. function = "uart";
  98. };
  99. uart2_pins: uart2-pins {
  100. pins = "GPIO_13", "GPIO_14";
  101. function = "uart2";
  102. };
  103. cs1_pins: cs1-pins {
  104. pins = "GPIO_8";
  105. function = "si";
  106. };
  107. irqext0_pins: irqext0-pins {
  108. pins = "GPIO_28";
  109. function = "irq0";
  110. };
  111. irqext1_pins: irqext1-pins {
  112. pins = "GPIO_29";
  113. function = "irq1";
  114. };
  115. };
  116. i2c0: i2c@70100400 {
  117. compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
  118. status = "disabled";
  119. pinctrl-0 = <&i2c_pins>;
  120. pinctrl-names = "default";
  121. reg = <0x70100400 0x100>, <0x70000190 0x8>;
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. interrupts = <8>;
  125. clock-frequency = <100000>;
  126. clocks = <&ahb_clk>;
  127. };
  128. };
  129. };