jaguar2.dtsi 3.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2020 Microsemi Corporation
  4. */
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. compatible = "mscc,jr2";
  9. aliases {
  10. serial0 = &uart0;
  11. serial1 = &uart2;
  12. gpio0 = &gpio;
  13. };
  14. cpus {
  15. #address-cells = <1>;
  16. #size-cells = <0>;
  17. cpu@0 {
  18. compatible = "mips,mips24KEc";
  19. device_type = "cpu";
  20. clocks = <&cpu_clk>;
  21. reg = <0>;
  22. };
  23. };
  24. cpuintc: interrupt-controller {
  25. #address-cells = <0>;
  26. #interrupt-cells = <1>;
  27. interrupt-controller;
  28. compatible = "mti,cpu-interrupt-controller";
  29. };
  30. cpu_clk: cpu-clock {
  31. compatible = "fixed-clock";
  32. #clock-cells = <0>;
  33. clock-frequency = <500000000>;
  34. };
  35. ahb_clk: ahb-clk {
  36. compatible = "fixed-factor-clock";
  37. #clock-cells = <0>;
  38. clocks = <&cpu_clk>;
  39. clock-div = <2>;
  40. clock-mult = <1>;
  41. };
  42. ahb: ahb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. interrupt-parent = <&intc>;
  48. cpu_ctrl: syscon@70000000 {
  49. compatible = "mscc,ocelot-cpu-syscon", "syscon";
  50. reg = <0x70000000 0x2c>;
  51. };
  52. intc: interrupt-controller@70000070 {
  53. compatible = "mscc,jaguar2-icpu-intr";
  54. reg = <0x70000070 0x94>;
  55. #interrupt-cells = <1>;
  56. interrupt-controller;
  57. interrupt-parent = <&cpuintc>;
  58. interrupts = <2>;
  59. };
  60. uart0: serial@70100000 {
  61. pinctrl-0 = <&uart_pins>;
  62. pinctrl-names = "default";
  63. compatible = "ns16550a";
  64. reg = <0x70100000 0x20>;
  65. interrupts = <6>;
  66. clocks = <&ahb_clk>;
  67. reg-io-width = <4>;
  68. reg-shift = <2>;
  69. status = "disabled";
  70. };
  71. uart2: serial@70100800 {
  72. pinctrl-0 = <&uart2_pins>;
  73. pinctrl-names = "default";
  74. compatible = "ns16550a";
  75. reg = <0x70100800 0x20>;
  76. interrupts = <7>;
  77. clocks = <&ahb_clk>;
  78. reg-io-width = <4>;
  79. reg-shift = <2>;
  80. status = "disabled";
  81. };
  82. gpio: pinctrl@71010038 {
  83. compatible = "mscc,jaguar2-pinctrl";
  84. reg = <0x71010038 0x90>;
  85. gpio-controller;
  86. #gpio-cells = <2>;
  87. gpio-ranges = <&gpio 0 0 64>;
  88. uart_pins: uart-pins {
  89. pins = "GPIO_10", "GPIO_11";
  90. function = "uart";
  91. };
  92. uart2_pins: uart2-pins {
  93. pins = "GPIO_24", "GPIO_25";
  94. function = "uart2";
  95. };
  96. cs1_pins: cs1-pins {
  97. pins = "GPIO_16";
  98. function = "si";
  99. };
  100. cs2_pins: cs2-pins {
  101. pins = "GPIO_17";
  102. function = "si";
  103. };
  104. cs3_pins: cs3-pins {
  105. pins = "GPIO_18";
  106. function = "si";
  107. };
  108. i2c_pins: i2c-pins {
  109. pins = "GPIO_14", "GPIO_15";
  110. function = "twi";
  111. };
  112. i2c2_pins: i2c2-pins {
  113. pins = "GPIO_28", "GPIO_29";
  114. function = "twi2";
  115. };
  116. };
  117. i2c0: i2c@70100400 {
  118. compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
  119. status = "disabled";
  120. pinctrl-0 = <&i2c_pins>;
  121. pinctrl-names = "default";
  122. reg = <0x70100400 0x100>, <0x700001b8 0x8>;
  123. #address-cells = <1>;
  124. #size-cells = <0>;
  125. interrupts = <8>;
  126. clock-frequency = <100000>;
  127. clocks = <&ahb_clk>;
  128. };
  129. i2c2: i2c@70100c00 {
  130. compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
  131. status = "disabled";
  132. pinctrl-0 = <&i2c2_pins>;
  133. pinctrl-names = "default";
  134. reg = <0x70100c00 0x100>;
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. interrupts = <8>;
  138. clock-frequency = <100000>;
  139. clocks = <&ahb_clk>;
  140. };
  141. };
  142. };