x1830.dtsi 8.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430
  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/clock/ingenic,tcu.h>
  3. #include <dt-bindings/clock/ingenic,x1830-cgu.h>
  4. #include <dt-bindings/dma/x1830-dma.h>
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. compatible = "ingenic,x1830";
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. cpu0: cpu@0 {
  13. device_type = "cpu";
  14. compatible = "ingenic,xburst-fpu2.0-mxu2.0";
  15. reg = <0>;
  16. clocks = <&cgu X1830_CLK_CPU>;
  17. clock-names = "cpu";
  18. };
  19. };
  20. cpuintc: interrupt-controller {
  21. #address-cells = <0>;
  22. #interrupt-cells = <1>;
  23. interrupt-controller;
  24. compatible = "mti,cpu-interrupt-controller";
  25. };
  26. intc: interrupt-controller@10001000 {
  27. compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
  28. reg = <0x10001000 0x50>;
  29. interrupt-controller;
  30. #interrupt-cells = <1>;
  31. interrupt-parent = <&cpuintc>;
  32. interrupts = <2>;
  33. };
  34. exclk: ext {
  35. compatible = "fixed-clock";
  36. #clock-cells = <0>;
  37. };
  38. rtclk: rtc {
  39. compatible = "fixed-clock";
  40. #clock-cells = <0>;
  41. clock-frequency = <32768>;
  42. };
  43. cgu: x1830-cgu@10000000 {
  44. compatible = "ingenic,x1830-cgu", "simple-mfd";
  45. reg = <0x10000000 0x100>;
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges = <0x0 0x10000000 0x100>;
  49. #clock-cells = <1>;
  50. clocks = <&exclk>, <&rtclk>;
  51. clock-names = "ext", "rtc";
  52. otg_phy: usb-phy@3c {
  53. compatible = "ingenic,x1830-phy";
  54. reg = <0x3c 0x10>;
  55. clocks = <&cgu X1830_CLK_OTGPHY>;
  56. #phy-cells = <0>;
  57. status = "disabled";
  58. };
  59. mac_phy_ctrl: mac-phy-ctrl@e8 {
  60. compatible = "syscon";
  61. reg = <0xe8 0x4>;
  62. };
  63. };
  64. ost: timer@12000000 {
  65. compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
  66. reg = <0x12000000 0x3c>;
  67. #clock-cells = <1>;
  68. clocks = <&cgu X1830_CLK_OST>;
  69. clock-names = "ost";
  70. interrupt-parent = <&cpuintc>;
  71. interrupts = <4>;
  72. };
  73. tcu: timer@10002000 {
  74. compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
  75. reg = <0x10002000 0x1000>;
  76. #address-cells = <1>;
  77. #size-cells = <1>;
  78. ranges = <0x0 0x10002000 0x1000>;
  79. #clock-cells = <1>;
  80. clocks = <&cgu X1830_CLK_RTCLK>,
  81. <&cgu X1830_CLK_EXCLK>,
  82. <&cgu X1830_CLK_PCLK>,
  83. <&cgu X1830_CLK_TCU>;
  84. clock-names = "rtc", "ext", "pclk", "tcu";
  85. interrupt-controller;
  86. #interrupt-cells = <1>;
  87. interrupt-parent = <&intc>;
  88. interrupts = <27 26 25>;
  89. wdt: watchdog@0 {
  90. compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
  91. reg = <0x0 0x10>;
  92. clocks = <&tcu TCU_CLK_WDT>;
  93. clock-names = "wdt";
  94. };
  95. pwm: pwm@40 {
  96. compatible = "ingenic,x1830-pwm", "ingenic,jz4740-pwm";
  97. reg = <0x40 0x80>;
  98. #pwm-cells = <3>;
  99. clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
  100. <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
  101. <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
  102. <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
  103. clock-names = "timer0", "timer1", "timer2", "timer3",
  104. "timer4", "timer5", "timer6", "timer7";
  105. };
  106. };
  107. rtc: rtc@10003000 {
  108. compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
  109. reg = <0x10003000 0x4c>;
  110. interrupt-parent = <&intc>;
  111. interrupts = <32>;
  112. clocks = <&cgu X1830_CLK_RTCLK>;
  113. clock-names = "rtc";
  114. };
  115. pinctrl: pin-controller@10010000 {
  116. compatible = "ingenic,x1830-pinctrl";
  117. reg = <0x10010000 0x800>;
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. gpa: gpio@0 {
  121. compatible = "ingenic,x1830-gpio";
  122. reg = <0>;
  123. gpio-controller;
  124. gpio-ranges = <&pinctrl 0 0 32>;
  125. #gpio-cells = <2>;
  126. interrupt-controller;
  127. #interrupt-cells = <2>;
  128. interrupt-parent = <&intc>;
  129. interrupts = <17>;
  130. };
  131. gpb: gpio@1 {
  132. compatible = "ingenic,x1830-gpio";
  133. reg = <1>;
  134. gpio-controller;
  135. gpio-ranges = <&pinctrl 0 32 32>;
  136. #gpio-cells = <2>;
  137. interrupt-controller;
  138. #interrupt-cells = <2>;
  139. interrupt-parent = <&intc>;
  140. interrupts = <16>;
  141. };
  142. gpc: gpio@2 {
  143. compatible = "ingenic,x1830-gpio";
  144. reg = <2>;
  145. gpio-controller;
  146. gpio-ranges = <&pinctrl 0 64 32>;
  147. #gpio-cells = <2>;
  148. interrupt-controller;
  149. #interrupt-cells = <2>;
  150. interrupt-parent = <&intc>;
  151. interrupts = <15>;
  152. };
  153. gpd: gpio@3 {
  154. compatible = "ingenic,x1830-gpio";
  155. reg = <3>;
  156. gpio-controller;
  157. gpio-ranges = <&pinctrl 0 96 32>;
  158. #gpio-cells = <2>;
  159. interrupt-controller;
  160. #interrupt-cells = <2>;
  161. interrupt-parent = <&intc>;
  162. interrupts = <14>;
  163. };
  164. };
  165. uart0: serial@10030000 {
  166. compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
  167. reg = <0x10030000 0x100>;
  168. interrupt-parent = <&intc>;
  169. interrupts = <51>;
  170. clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
  171. clock-names = "baud", "module";
  172. status = "disabled";
  173. };
  174. uart1: serial@10031000 {
  175. compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
  176. reg = <0x10031000 0x100>;
  177. interrupt-parent = <&intc>;
  178. interrupts = <50>;
  179. clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
  180. clock-names = "baud", "module";
  181. status = "disabled";
  182. };
  183. ssi0: spi@10043000 {
  184. compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
  185. reg = <0x10043000 0x20>;
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. interrupt-parent = <&intc>;
  189. interrupts = <9>;
  190. clocks = <&cgu X1830_CLK_SSI0>;
  191. clock-names = "spi";
  192. dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>,
  193. <&pdma X1830_DMA_SSI0_TX 0xffffffff>;
  194. dma-names = "rx", "tx";
  195. status = "disabled";
  196. };
  197. ssi1: spi@10044000 {
  198. compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
  199. reg = <0x10044000 0x20>;
  200. #address-cells = <1>;
  201. #size-cells = <0>;
  202. interrupt-parent = <&intc>;
  203. interrupts = <8>;
  204. clocks = <&cgu X1830_CLK_SSI1>;
  205. clock-names = "spi";
  206. dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>,
  207. <&pdma X1830_DMA_SSI1_TX 0xffffffff>;
  208. dma-names = "rx", "tx";
  209. status = "disabled";
  210. };
  211. i2c0: i2c-controller@10050000 {
  212. compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
  213. reg = <0x10050000 0x1000>;
  214. #address-cells = <1>;
  215. #size-cells = <0>;
  216. interrupt-parent = <&intc>;
  217. interrupts = <60>;
  218. clocks = <&cgu X1830_CLK_SMB0>;
  219. status = "disabled";
  220. };
  221. i2c1: i2c-controller@10051000 {
  222. compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
  223. reg = <0x10051000 0x1000>;
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. interrupt-parent = <&intc>;
  227. interrupts = <59>;
  228. clocks = <&cgu X1830_CLK_SMB1>;
  229. status = "disabled";
  230. };
  231. i2c2: i2c-controller@10052000 {
  232. compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
  233. reg = <0x10052000 0x1000>;
  234. #address-cells = <1>;
  235. #size-cells = <0>;
  236. interrupt-parent = <&intc>;
  237. interrupts = <58>;
  238. clocks = <&cgu X1830_CLK_SMB2>;
  239. status = "disabled";
  240. };
  241. dtrng: trng@10072000 {
  242. compatible = "ingenic,x1830-dtrng";
  243. reg = <0x10072000 0xc>;
  244. clocks = <&cgu X1830_CLK_DTRNG>;
  245. status = "disabled";
  246. };
  247. pdma: dma-controller@13420000 {
  248. compatible = "ingenic,x1830-dma";
  249. reg = <0x13420000 0x400>, <0x13421000 0x40>;
  250. #dma-cells = <2>;
  251. interrupt-parent = <&intc>;
  252. interrupts = <10>;
  253. clocks = <&cgu X1830_CLK_PDMA>;
  254. };
  255. msc0: mmc@13450000 {
  256. compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
  257. reg = <0x13450000 0x1000>;
  258. interrupt-parent = <&intc>;
  259. interrupts = <37>;
  260. clocks = <&cgu X1830_CLK_MSC0>;
  261. clock-names = "mmc";
  262. cap-sd-highspeed;
  263. cap-mmc-highspeed;
  264. cap-sdio-irq;
  265. dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
  266. <&pdma X1830_DMA_MSC0_TX 0xffffffff>;
  267. dma-names = "rx", "tx";
  268. status = "disabled";
  269. };
  270. msc1: mmc@13460000 {
  271. compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
  272. reg = <0x13460000 0x1000>;
  273. interrupt-parent = <&intc>;
  274. interrupts = <36>;
  275. clocks = <&cgu X1830_CLK_MSC1>;
  276. clock-names = "mmc";
  277. cap-sd-highspeed;
  278. cap-mmc-highspeed;
  279. cap-sdio-irq;
  280. dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
  281. <&pdma X1830_DMA_MSC1_TX 0xffffffff>;
  282. dma-names = "rx", "tx";
  283. status = "disabled";
  284. };
  285. mac: ethernet@134b0000 {
  286. compatible = "ingenic,x1830-mac", "snps,dwmac";
  287. reg = <0x134b0000 0x2000>;
  288. interrupt-parent = <&intc>;
  289. interrupts = <55>;
  290. interrupt-names = "macirq";
  291. clocks = <&cgu X1830_CLK_MAC>;
  292. clock-names = "stmmaceth";
  293. mode-reg = <&mac_phy_ctrl>;
  294. status = "disabled";
  295. mdio: mdio {
  296. compatible = "snps,dwmac-mdio";
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. status = "disabled";
  300. };
  301. };
  302. otg: usb@13500000 {
  303. compatible = "ingenic,x1830-otg";
  304. reg = <0x13500000 0x40000>;
  305. interrupt-parent = <&intc>;
  306. interrupts = <21>;
  307. clocks = <&cgu X1830_CLK_OTG>;
  308. clock-names = "otg";
  309. phys = <&otg_phy>;
  310. phy-names = "usb2-phy";
  311. g-rx-fifo-size = <768>;
  312. g-np-tx-fifo-size = <256>;
  313. g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
  314. status = "disabled";
  315. };
  316. };