x1000.dtsi 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/clock/ingenic,tcu.h>
  3. #include <dt-bindings/clock/ingenic,x1000-cgu.h>
  4. #include <dt-bindings/dma/x1000-dma.h>
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. compatible = "ingenic,x1000", "ingenic,x1000e";
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. cpu0: cpu@0 {
  13. device_type = "cpu";
  14. compatible = "ingenic,xburst-fpu1.0-mxu1.1";
  15. reg = <0>;
  16. clocks = <&cgu X1000_CLK_CPU>;
  17. clock-names = "cpu";
  18. };
  19. };
  20. cpuintc: interrupt-controller {
  21. #address-cells = <0>;
  22. #interrupt-cells = <1>;
  23. interrupt-controller;
  24. compatible = "mti,cpu-interrupt-controller";
  25. };
  26. intc: interrupt-controller@10001000 {
  27. compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
  28. reg = <0x10001000 0x50>;
  29. interrupt-controller;
  30. #interrupt-cells = <1>;
  31. interrupt-parent = <&cpuintc>;
  32. interrupts = <2>;
  33. };
  34. exclk: ext {
  35. compatible = "fixed-clock";
  36. #clock-cells = <0>;
  37. };
  38. rtclk: rtc {
  39. compatible = "fixed-clock";
  40. #clock-cells = <0>;
  41. clock-frequency = <32768>;
  42. };
  43. cgu: x1000-cgu@10000000 {
  44. compatible = "ingenic,x1000-cgu", "simple-mfd";
  45. reg = <0x10000000 0x100>;
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges = <0x0 0x10000000 0x100>;
  49. #clock-cells = <1>;
  50. clocks = <&exclk>, <&rtclk>;
  51. clock-names = "ext", "rtc";
  52. otg_phy: usb-phy@3c {
  53. compatible = "ingenic,x1000-phy";
  54. reg = <0x3c 0x10>;
  55. clocks = <&cgu X1000_CLK_OTGPHY>;
  56. #phy-cells = <0>;
  57. status = "disabled";
  58. };
  59. rng: rng@d8 {
  60. compatible = "ingenic,x1000-rng";
  61. reg = <0xd8 0x8>;
  62. status = "disabled";
  63. };
  64. mac_phy_ctrl: mac-phy-ctrl@e8 {
  65. compatible = "syscon";
  66. reg = <0xe8 0x4>;
  67. };
  68. };
  69. ost: timer@12000000 {
  70. compatible = "ingenic,x1000-ost";
  71. reg = <0x12000000 0x3c>;
  72. #clock-cells = <1>;
  73. clocks = <&cgu X1000_CLK_OST>;
  74. clock-names = "ost";
  75. interrupt-parent = <&cpuintc>;
  76. interrupts = <3>;
  77. };
  78. tcu: timer@10002000 {
  79. compatible = "ingenic,x1000-tcu", "simple-mfd";
  80. reg = <0x10002000 0x1000>;
  81. #address-cells = <1>;
  82. #size-cells = <1>;
  83. ranges = <0x0 0x10002000 0x1000>;
  84. #clock-cells = <1>;
  85. clocks = <&cgu X1000_CLK_RTCLK>,
  86. <&cgu X1000_CLK_EXCLK>,
  87. <&cgu X1000_CLK_PCLK>,
  88. <&cgu X1000_CLK_TCU>;
  89. clock-names = "rtc", "ext", "pclk", "tcu";
  90. interrupt-controller;
  91. #interrupt-cells = <1>;
  92. interrupt-parent = <&intc>;
  93. interrupts = <27 26 25>;
  94. wdt: watchdog@0 {
  95. compatible = "ingenic,x1000-watchdog", "ingenic,jz4780-watchdog";
  96. reg = <0x0 0x10>;
  97. clocks = <&tcu TCU_CLK_WDT>;
  98. clock-names = "wdt";
  99. };
  100. pwm: pwm@40 {
  101. compatible = "ingenic,x1000-pwm";
  102. reg = <0x40 0x50>;
  103. #pwm-cells = <3>;
  104. clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
  105. <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
  106. <&tcu TCU_CLK_TIMER4>;
  107. clock-names = "timer0", "timer1", "timer2", "timer3", "timer4";
  108. };
  109. };
  110. rtc: rtc@10003000 {
  111. compatible = "ingenic,x1000-rtc", "ingenic,jz4780-rtc";
  112. reg = <0x10003000 0x4c>;
  113. interrupt-parent = <&intc>;
  114. interrupts = <32>;
  115. clocks = <&cgu X1000_CLK_RTCLK>;
  116. clock-names = "rtc";
  117. };
  118. pinctrl: pin-controller@10010000 {
  119. compatible = "ingenic,x1000-pinctrl";
  120. reg = <0x10010000 0x800>;
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. gpa: gpio@0 {
  124. compatible = "ingenic,x1000-gpio";
  125. reg = <0>;
  126. gpio-controller;
  127. gpio-ranges = <&pinctrl 0 0 32>;
  128. #gpio-cells = <2>;
  129. interrupt-controller;
  130. #interrupt-cells = <2>;
  131. interrupt-parent = <&intc>;
  132. interrupts = <17>;
  133. };
  134. gpb: gpio@1 {
  135. compatible = "ingenic,x1000-gpio";
  136. reg = <1>;
  137. gpio-controller;
  138. gpio-ranges = <&pinctrl 0 32 32>;
  139. #gpio-cells = <2>;
  140. interrupt-controller;
  141. #interrupt-cells = <2>;
  142. interrupt-parent = <&intc>;
  143. interrupts = <16>;
  144. };
  145. gpc: gpio@2 {
  146. compatible = "ingenic,x1000-gpio";
  147. reg = <2>;
  148. gpio-controller;
  149. gpio-ranges = <&pinctrl 0 64 32>;
  150. #gpio-cells = <2>;
  151. interrupt-controller;
  152. #interrupt-cells = <2>;
  153. interrupt-parent = <&intc>;
  154. interrupts = <15>;
  155. };
  156. gpd: gpio@3 {
  157. compatible = "ingenic,x1000-gpio";
  158. reg = <3>;
  159. gpio-controller;
  160. gpio-ranges = <&pinctrl 0 96 32>;
  161. #gpio-cells = <2>;
  162. interrupt-controller;
  163. #interrupt-cells = <2>;
  164. interrupt-parent = <&intc>;
  165. interrupts = <14>;
  166. };
  167. };
  168. uart0: serial@10030000 {
  169. compatible = "ingenic,x1000-uart";
  170. reg = <0x10030000 0x100>;
  171. interrupt-parent = <&intc>;
  172. interrupts = <51>;
  173. clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
  174. clock-names = "baud", "module";
  175. status = "disabled";
  176. };
  177. uart1: serial@10031000 {
  178. compatible = "ingenic,x1000-uart";
  179. reg = <0x10031000 0x100>;
  180. interrupt-parent = <&intc>;
  181. interrupts = <50>;
  182. clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
  183. clock-names = "baud", "module";
  184. status = "disabled";
  185. };
  186. uart2: serial@10032000 {
  187. compatible = "ingenic,x1000-uart";
  188. reg = <0x10032000 0x100>;
  189. interrupt-parent = <&intc>;
  190. interrupts = <49>;
  191. clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
  192. clock-names = "baud", "module";
  193. status = "disabled";
  194. };
  195. ssi: spi@10043000 {
  196. compatible = "ingenic,x1000-spi";
  197. reg = <0x10043000 0x20>;
  198. #address-cells = <1>;
  199. #size-cells = <0>;
  200. interrupt-parent = <&intc>;
  201. interrupts = <8>;
  202. clocks = <&cgu X1000_CLK_SSI>;
  203. clock-names = "spi";
  204. dmas = <&pdma X1000_DMA_SSI0_RX 0xffffffff>,
  205. <&pdma X1000_DMA_SSI0_TX 0xffffffff>;
  206. dma-names = "rx", "tx";
  207. status = "disabled";
  208. };
  209. i2c0: i2c-controller@10050000 {
  210. compatible = "ingenic,x1000-i2c";
  211. reg = <0x10050000 0x1000>;
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. interrupt-parent = <&intc>;
  215. interrupts = <60>;
  216. clocks = <&cgu X1000_CLK_I2C0>;
  217. status = "disabled";
  218. };
  219. i2c1: i2c-controller@10051000 {
  220. compatible = "ingenic,x1000-i2c";
  221. reg = <0x10051000 0x1000>;
  222. #address-cells = <1>;
  223. #size-cells = <0>;
  224. interrupt-parent = <&intc>;
  225. interrupts = <59>;
  226. clocks = <&cgu X1000_CLK_I2C1>;
  227. status = "disabled";
  228. };
  229. i2c2: i2c-controller@10052000 {
  230. compatible = "ingenic,x1000-i2c";
  231. reg = <0x10052000 0x1000>;
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234. interrupt-parent = <&intc>;
  235. interrupts = <58>;
  236. clocks = <&cgu X1000_CLK_I2C2>;
  237. status = "disabled";
  238. };
  239. pdma: dma-controller@13420000 {
  240. compatible = "ingenic,x1000-dma";
  241. reg = <0x13420000 0x400>, <0x13421000 0x40>;
  242. #dma-cells = <2>;
  243. interrupt-parent = <&intc>;
  244. interrupts = <10>;
  245. clocks = <&cgu X1000_CLK_PDMA>;
  246. };
  247. msc0: mmc@13450000 {
  248. compatible = "ingenic,x1000-mmc";
  249. reg = <0x13450000 0x1000>;
  250. interrupt-parent = <&intc>;
  251. interrupts = <37>;
  252. clocks = <&cgu X1000_CLK_MSC0>;
  253. clock-names = "mmc";
  254. cap-sd-highspeed;
  255. cap-mmc-highspeed;
  256. cap-sdio-irq;
  257. dmas = <&pdma X1000_DMA_MSC0_RX 0xffffffff>,
  258. <&pdma X1000_DMA_MSC0_TX 0xffffffff>;
  259. dma-names = "rx", "tx";
  260. status = "disabled";
  261. };
  262. msc1: mmc@13460000 {
  263. compatible = "ingenic,x1000-mmc";
  264. reg = <0x13460000 0x1000>;
  265. interrupt-parent = <&intc>;
  266. interrupts = <36>;
  267. clocks = <&cgu X1000_CLK_MSC1>;
  268. clock-names = "mmc";
  269. cap-sd-highspeed;
  270. cap-mmc-highspeed;
  271. cap-sdio-irq;
  272. dmas = <&pdma X1000_DMA_MSC1_RX 0xffffffff>,
  273. <&pdma X1000_DMA_MSC1_TX 0xffffffff>;
  274. dma-names = "rx", "tx";
  275. status = "disabled";
  276. };
  277. mac: ethernet@134b0000 {
  278. compatible = "ingenic,x1000-mac", "snps,dwmac";
  279. reg = <0x134b0000 0x2000>;
  280. interrupt-parent = <&intc>;
  281. interrupts = <55>;
  282. interrupt-names = "macirq";
  283. clocks = <&cgu X1000_CLK_MAC>;
  284. clock-names = "stmmaceth";
  285. mode-reg = <&mac_phy_ctrl>;
  286. status = "disabled";
  287. mdio: mdio {
  288. compatible = "snps,dwmac-mdio";
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. status = "disabled";
  292. };
  293. };
  294. otg: usb@13500000 {
  295. compatible = "ingenic,x1000-otg";
  296. reg = <0x13500000 0x40000>;
  297. interrupt-parent = <&intc>;
  298. interrupts = <21>;
  299. clocks = <&cgu X1000_CLK_OTG>;
  300. clock-names = "otg";
  301. phys = <&otg_phy>;
  302. phy-names = "usb2-phy";
  303. g-rx-fifo-size = <768>;
  304. g-np-tx-fifo-size = <256>;
  305. g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
  306. status = "disabled";
  307. };
  308. };