jz4740.dtsi 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
  3. #include <dt-bindings/clock/ingenic,tcu.h>
  4. / {
  5. #address-cells = <1>;
  6. #size-cells = <1>;
  7. compatible = "ingenic,jz4740";
  8. cpus {
  9. #address-cells = <1>;
  10. #size-cells = <0>;
  11. cpu0: cpu@0 {
  12. device_type = "cpu";
  13. compatible = "ingenic,xburst-mxu1.0";
  14. reg = <0>;
  15. clocks = <&cgu JZ4740_CLK_CCLK>;
  16. clock-names = "cpu";
  17. };
  18. };
  19. cpuintc: interrupt-controller {
  20. #address-cells = <0>;
  21. #interrupt-cells = <1>;
  22. interrupt-controller;
  23. compatible = "mti,cpu-interrupt-controller";
  24. };
  25. intc: interrupt-controller@10001000 {
  26. compatible = "ingenic,jz4740-intc";
  27. reg = <0x10001000 0x14>;
  28. interrupt-controller;
  29. #interrupt-cells = <1>;
  30. interrupt-parent = <&cpuintc>;
  31. interrupts = <2>;
  32. };
  33. ext: ext {
  34. compatible = "fixed-clock";
  35. #clock-cells = <0>;
  36. };
  37. rtc: rtc {
  38. compatible = "fixed-clock";
  39. #clock-cells = <0>;
  40. clock-frequency = <32768>;
  41. };
  42. cgu: jz4740-cgu@10000000 {
  43. compatible = "ingenic,jz4740-cgu";
  44. reg = <0x10000000 0x100>;
  45. clocks = <&ext>, <&rtc>;
  46. clock-names = "ext", "rtc";
  47. #clock-cells = <1>;
  48. };
  49. tcu: timer@10002000 {
  50. compatible = "ingenic,jz4740-tcu", "simple-mfd";
  51. reg = <0x10002000 0x1000>;
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. ranges = <0x0 0x10002000 0x1000>;
  55. #clock-cells = <1>;
  56. clocks = <&cgu JZ4740_CLK_RTC>,
  57. <&cgu JZ4740_CLK_EXT>,
  58. <&cgu JZ4740_CLK_PCLK>,
  59. <&cgu JZ4740_CLK_TCU>;
  60. clock-names = "rtc", "ext", "pclk", "tcu";
  61. interrupt-controller;
  62. #interrupt-cells = <1>;
  63. interrupt-parent = <&intc>;
  64. interrupts = <23 22 21>;
  65. watchdog: watchdog@0 {
  66. compatible = "ingenic,jz4740-watchdog";
  67. reg = <0x0 0xc>;
  68. clocks = <&tcu TCU_CLK_WDT>;
  69. clock-names = "wdt";
  70. };
  71. pwm: pwm@40 {
  72. compatible = "ingenic,jz4740-pwm";
  73. reg = <0x40 0x80>;
  74. #pwm-cells = <3>;
  75. clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
  76. <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
  77. <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
  78. <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
  79. clock-names = "timer0", "timer1", "timer2", "timer3",
  80. "timer4", "timer5", "timer6", "timer7";
  81. };
  82. };
  83. rtc_dev: rtc@10003000 {
  84. compatible = "ingenic,jz4740-rtc";
  85. reg = <0x10003000 0x40>;
  86. interrupt-parent = <&intc>;
  87. interrupts = <15>;
  88. clocks = <&cgu JZ4740_CLK_RTC>;
  89. clock-names = "rtc";
  90. };
  91. pinctrl: pin-controller@10010000 {
  92. compatible = "ingenic,jz4740-pinctrl";
  93. reg = <0x10010000 0x400>;
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96. gpa: gpio@0 {
  97. compatible = "ingenic,jz4740-gpio";
  98. reg = <0>;
  99. gpio-controller;
  100. gpio-ranges = <&pinctrl 0 0 32>;
  101. #gpio-cells = <2>;
  102. interrupt-controller;
  103. #interrupt-cells = <2>;
  104. interrupt-parent = <&intc>;
  105. interrupts = <28>;
  106. };
  107. gpb: gpio@1 {
  108. compatible = "ingenic,jz4740-gpio";
  109. reg = <1>;
  110. gpio-controller;
  111. gpio-ranges = <&pinctrl 0 32 32>;
  112. #gpio-cells = <2>;
  113. interrupt-controller;
  114. #interrupt-cells = <2>;
  115. interrupt-parent = <&intc>;
  116. interrupts = <27>;
  117. };
  118. gpc: gpio@2 {
  119. compatible = "ingenic,jz4740-gpio";
  120. reg = <2>;
  121. gpio-controller;
  122. gpio-ranges = <&pinctrl 0 64 32>;
  123. #gpio-cells = <2>;
  124. interrupt-controller;
  125. #interrupt-cells = <2>;
  126. interrupt-parent = <&intc>;
  127. interrupts = <26>;
  128. };
  129. gpd: gpio@3 {
  130. compatible = "ingenic,jz4740-gpio";
  131. reg = <3>;
  132. gpio-controller;
  133. gpio-ranges = <&pinctrl 0 96 32>;
  134. #gpio-cells = <2>;
  135. interrupt-controller;
  136. #interrupt-cells = <2>;
  137. interrupt-parent = <&intc>;
  138. interrupts = <25>;
  139. };
  140. };
  141. aic: audio-controller@10020000 {
  142. compatible = "ingenic,jz4740-i2s";
  143. reg = <0x10020000 0x38>;
  144. #sound-dai-cells = <0>;
  145. interrupt-parent = <&intc>;
  146. interrupts = <18>;
  147. clocks = <&cgu JZ4740_CLK_AIC>,
  148. <&cgu JZ4740_CLK_I2S>,
  149. <&cgu JZ4740_CLK_EXT>,
  150. <&cgu JZ4740_CLK_PLL_HALF>;
  151. clock-names = "aic", "i2s", "ext", "pll half";
  152. dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
  153. dma-names = "rx", "tx";
  154. };
  155. codec: audio-codec@100200a4 {
  156. compatible = "ingenic,jz4740-codec";
  157. reg = <0x10020080 0x8>;
  158. #sound-dai-cells = <0>;
  159. clocks = <&cgu JZ4740_CLK_AIC>;
  160. clock-names = "aic";
  161. };
  162. mmc: mmc@10021000 {
  163. compatible = "ingenic,jz4740-mmc";
  164. reg = <0x10021000 0x1000>;
  165. clocks = <&cgu JZ4740_CLK_MMC>;
  166. clock-names = "mmc";
  167. interrupt-parent = <&intc>;
  168. interrupts = <14>;
  169. dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
  170. dma-names = "rx", "tx";
  171. cap-sd-highspeed;
  172. cap-mmc-highspeed;
  173. cap-sdio-irq;
  174. };
  175. uart0: serial@10030000 {
  176. compatible = "ingenic,jz4740-uart";
  177. reg = <0x10030000 0x100>;
  178. interrupt-parent = <&intc>;
  179. interrupts = <9>;
  180. clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
  181. clock-names = "baud", "module";
  182. };
  183. uart1: serial@10031000 {
  184. compatible = "ingenic,jz4740-uart";
  185. reg = <0x10031000 0x100>;
  186. interrupt-parent = <&intc>;
  187. interrupts = <8>;
  188. clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
  189. clock-names = "baud", "module";
  190. };
  191. adc: adc@10070000 {
  192. compatible = "ingenic,jz4740-adc";
  193. reg = <0x10070000 0x30>;
  194. #io-channel-cells = <1>;
  195. clocks = <&cgu JZ4740_CLK_ADC>;
  196. clock-names = "adc";
  197. interrupt-parent = <&intc>;
  198. interrupts = <12>;
  199. };
  200. nemc: memory-controller@13010000 {
  201. compatible = "ingenic,jz4740-nemc";
  202. reg = <0x13010000 0x54>;
  203. #address-cells = <2>;
  204. #size-cells = <1>;
  205. ranges = <1 0 0x18000000 0x4000000>,
  206. <2 0 0x14000000 0x4000000>,
  207. <3 0 0x0c000000 0x4000000>,
  208. <4 0 0x08000000 0x4000000>;
  209. clocks = <&cgu JZ4740_CLK_MCLK>;
  210. };
  211. ecc: ecc-controller@13010100 {
  212. compatible = "ingenic,jz4740-ecc";
  213. reg = <0x13010100 0x2C>;
  214. clocks = <&cgu JZ4740_CLK_MCLK>;
  215. };
  216. dmac: dma-controller@13020000 {
  217. compatible = "ingenic,jz4740-dma";
  218. reg = <0x13020000 0xbc>, <0x13020300 0x14>;
  219. #dma-cells = <2>;
  220. interrupt-parent = <&intc>;
  221. interrupts = <20>;
  222. clocks = <&cgu JZ4740_CLK_DMA>;
  223. };
  224. uhc: usb@13030000 {
  225. compatible = "ingenic,jz4740-ohci", "generic-ohci";
  226. reg = <0x13030000 0x1000>;
  227. clocks = <&cgu JZ4740_CLK_UHC>;
  228. assigned-clocks = <&cgu JZ4740_CLK_UHC>;
  229. assigned-clock-rates = <48000000>;
  230. interrupt-parent = <&intc>;
  231. interrupts = <3>;
  232. status = "disabled";
  233. };
  234. udc: usb@13040000 {
  235. compatible = "ingenic,jz4740-musb";
  236. reg = <0x13040000 0x10000>;
  237. interrupt-parent = <&intc>;
  238. interrupts = <24>;
  239. interrupt-names = "mc";
  240. clocks = <&cgu JZ4740_CLK_UDC>;
  241. clock-names = "udc";
  242. };
  243. lcd: lcd-controller@13050000 {
  244. compatible = "ingenic,jz4740-lcd";
  245. reg = <0x13050000 0x60>; /* LCDCMD1+4 */
  246. interrupt-parent = <&intc>;
  247. interrupts = <30>;
  248. clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
  249. clock-names = "lcd_pclk", "lcd";
  250. };
  251. };