bcm6362.dtsi 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include "dt-bindings/clock/bcm6362-clock.h"
  3. #include "dt-bindings/reset/bcm6362-reset.h"
  4. #include "dt-bindings/soc/bcm6362-pm.h"
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. compatible = "brcm,bcm6362";
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. mips-hpt-frequency = <200000000>;
  13. cpu@0 {
  14. compatible = "brcm,bmips4350";
  15. device_type = "cpu";
  16. reg = <0>;
  17. };
  18. cpu@1 {
  19. compatible = "brcm,bmips4350";
  20. device_type = "cpu";
  21. reg = <1>;
  22. };
  23. };
  24. clocks {
  25. periph_osc: periph-osc {
  26. compatible = "fixed-clock";
  27. #clock-cells = <0>;
  28. clock-frequency = <50000000>;
  29. clock-output-names = "periph";
  30. };
  31. hsspi_osc: hsspi-osc {
  32. compatible = "fixed-clock";
  33. #clock-cells = <0>;
  34. clock-frequency = <400000000>;
  35. clock-output-names = "hsspi_osc";
  36. };
  37. };
  38. aliases {
  39. nflash = &nflash;
  40. serial0 = &uart0;
  41. serial1 = &uart1;
  42. spi0 = &lsspi;
  43. spi1 = &hsspi;
  44. };
  45. cpu_intc: interrupt-controller {
  46. #address-cells = <0>;
  47. compatible = "mti,cpu-interrupt-controller";
  48. interrupt-controller;
  49. #interrupt-cells = <1>;
  50. };
  51. ubus {
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. compatible = "simple-bus";
  55. ranges;
  56. periph_clk: clock-controller@10000004 {
  57. compatible = "brcm,bcm6362-clocks";
  58. reg = <0x10000004 0x4>;
  59. #clock-cells = <1>;
  60. };
  61. pll_cntl: syscon@10000008 {
  62. compatible = "syscon";
  63. reg = <0x10000008 0x4>;
  64. native-endian;
  65. reboot {
  66. compatible = "syscon-reboot";
  67. offset = <0x0>;
  68. mask = <0x1>;
  69. };
  70. };
  71. periph_rst: reset-controller@10000010 {
  72. compatible = "brcm,bcm6345-reset";
  73. reg = <0x10000010 0x4>;
  74. #reset-cells = <1>;
  75. };
  76. periph_intc: interrupt-controller@10000020 {
  77. compatible = "brcm,bcm6345-l1-intc";
  78. reg = <0x10000020 0x10>,
  79. <0x10000030 0x10>;
  80. interrupt-controller;
  81. #interrupt-cells = <1>;
  82. interrupt-parent = <&cpu_intc>;
  83. interrupts = <2>, <3>;
  84. };
  85. wdt: watchdog@1000005c {
  86. compatible = "brcm,bcm7038-wdt";
  87. reg = <0x1000005c 0xc>;
  88. clocks = <&periph_osc>;
  89. clock-names = "refclk";
  90. timeout-sec = <30>;
  91. };
  92. uart0: serial@10000100 {
  93. compatible = "brcm,bcm6345-uart";
  94. reg = <0x10000100 0x18>;
  95. interrupt-parent = <&periph_intc>;
  96. interrupts = <3>;
  97. clocks = <&periph_osc>;
  98. clock-names = "refclk";
  99. status = "disabled";
  100. };
  101. uart1: serial@10000120 {
  102. compatible = "brcm,bcm6345-uart";
  103. reg = <0x10000120 0x18>;
  104. interrupt-parent = <&periph_intc>;
  105. interrupts = <4>;
  106. clocks = <&periph_osc>;
  107. clock-names = "refclk";
  108. status = "disabled";
  109. };
  110. nflash: nand@10000200 {
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. compatible = "brcm,nand-bcm6368",
  114. "brcm,brcmnand-v2.2",
  115. "brcm,brcmnand";
  116. reg = <0x10000200 0x180>,
  117. <0x10000600 0x200>,
  118. <0x10000070 0x10>;
  119. reg-names = "nand",
  120. "nand-cache",
  121. "nand-int-base";
  122. interrupt-parent = <&periph_intc>;
  123. interrupts = <12>;
  124. clocks = <&periph_clk BCM6362_CLK_NAND>;
  125. clock-names = "nand";
  126. status = "disabled";
  127. };
  128. lsspi: spi@10000800 {
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. compatible = "brcm,bcm6358-spi";
  132. reg = <0x10000800 0x70c>;
  133. interrupt-parent = <&periph_intc>;
  134. interrupts = <2>;
  135. clocks = <&periph_clk BCM6362_CLK_SPI>;
  136. clock-names = "spi";
  137. resets = <&periph_rst BCM6362_RST_SPI>;
  138. reset-names = "spi";
  139. status = "disabled";
  140. };
  141. hsspi: spi@10001000 {
  142. #address-cells = <1>;
  143. #size-cells = <0>;
  144. compatible = "brcm,bcm6328-hsspi";
  145. reg = <0x10001000 0x600>;
  146. interrupt-parent = <&periph_intc>;
  147. interrupts = <5>;
  148. clocks = <&periph_clk BCM6362_CLK_HSSPI>,
  149. <&hsspi_osc>;
  150. clock-names = "hsspi",
  151. "pll";
  152. resets = <&periph_rst BCM6362_RST_SPI>;
  153. reset-names = "hsspi";
  154. status = "disabled";
  155. };
  156. periph_pwr: power-controller@10001848 {
  157. compatible = "brcm,bcm6362-power-controller";
  158. reg = <0x10001848 0x4>;
  159. #power-domain-cells = <1>;
  160. };
  161. leds0: led-controller@10001900 {
  162. #address-cells = <1>;
  163. #size-cells = <0>;
  164. compatible = "brcm,bcm6328-leds";
  165. reg = <0x10001900 0x24>;
  166. status = "disabled";
  167. };
  168. ehci: usb@10002500 {
  169. compatible = "brcm,bcm6362-ehci", "generic-ehci";
  170. reg = <0x10002500 0x100>;
  171. big-endian;
  172. interrupt-parent = <&periph_intc>;
  173. interrupts = <10>;
  174. phys = <&usbh 0>;
  175. phy-names = "usb";
  176. status = "disabled";
  177. };
  178. ohci: usb@10002600 {
  179. compatible = "brcm,bcm6362-ohci", "generic-ohci";
  180. reg = <0x10002600 0x100>;
  181. big-endian;
  182. no-big-frame-no;
  183. interrupt-parent = <&periph_intc>;
  184. interrupts = <9>;
  185. phys = <&usbh 0>;
  186. phy-names = "usb";
  187. status = "disabled";
  188. };
  189. usbh: usb-phy@10002700 {
  190. compatible = "brcm,bcm6362-usbh-phy";
  191. reg = <0x10002700 0x38>;
  192. #phy-cells = <1>;
  193. clocks = <&periph_clk BCM6362_CLK_USBH>;
  194. clock-names = "usbh";
  195. power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>;
  196. resets = <&periph_rst BCM6362_RST_USBH>;
  197. reset-names = "usbh";
  198. status = "disabled";
  199. };
  200. };
  201. };