bcm6358.dtsi 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include "dt-bindings/clock/bcm6358-clock.h"
  3. #include "dt-bindings/reset/bcm6358-reset.h"
  4. / {
  5. #address-cells = <1>;
  6. #size-cells = <1>;
  7. compatible = "brcm,bcm6358";
  8. cpus {
  9. #address-cells = <1>;
  10. #size-cells = <0>;
  11. mips-hpt-frequency = <150000000>;
  12. cpu@0 {
  13. compatible = "brcm,bmips4350";
  14. device_type = "cpu";
  15. reg = <0>;
  16. };
  17. cpu@1 {
  18. compatible = "brcm,bmips4350";
  19. device_type = "cpu";
  20. reg = <1>;
  21. };
  22. };
  23. clocks {
  24. periph_osc: periph-osc {
  25. compatible = "fixed-clock";
  26. #clock-cells = <0>;
  27. clock-frequency = <50000000>;
  28. clock-output-names = "periph";
  29. };
  30. };
  31. aliases {
  32. pflash = &pflash;
  33. serial0 = &uart0;
  34. serial1 = &uart1;
  35. spi0 = &lsspi;
  36. };
  37. cpu_intc: interrupt-controller {
  38. #address-cells = <0>;
  39. compatible = "mti,cpu-interrupt-controller";
  40. interrupt-controller;
  41. #interrupt-cells = <1>;
  42. };
  43. ubus {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. compatible = "simple-bus";
  47. ranges;
  48. periph_clk: clock-controller@fffe0004 {
  49. compatible = "brcm,bcm6358-clocks";
  50. reg = <0xfffe0004 0x4>;
  51. #clock-cells = <1>;
  52. };
  53. pll_cntl: syscon@fffe0008 {
  54. compatible = "syscon";
  55. reg = <0xfffe0008 0x4>;
  56. native-endian;
  57. reboot {
  58. compatible = "syscon-reboot";
  59. offset = <0x0>;
  60. mask = <0x1>;
  61. };
  62. };
  63. periph_intc: interrupt-controller@fffe000c {
  64. compatible = "brcm,bcm6345-l1-intc";
  65. reg = <0xfffe000c 0x8>,
  66. <0xfffe0038 0x8>;
  67. interrupt-controller;
  68. #interrupt-cells = <1>;
  69. interrupt-parent = <&cpu_intc>;
  70. interrupts = <2>, <3>;
  71. };
  72. periph_rst: reset-controller@fffe0034 {
  73. compatible = "brcm,bcm6345-reset";
  74. reg = <0xfffe0034 0x4>;
  75. #reset-cells = <1>;
  76. };
  77. wdt: watchdog@fffe005c {
  78. compatible = "brcm,bcm7038-wdt";
  79. reg = <0xfffe005c 0xc>;
  80. clocks = <&periph_osc>;
  81. clock-names = "refclk";
  82. timeout-sec = <30>;
  83. };
  84. leds0: led-controller@fffe00d0 {
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. compatible = "brcm,bcm6358-leds";
  88. reg = <0xfffe00d0 0x8>;
  89. status = "disabled";
  90. };
  91. uart0: serial@fffe0100 {
  92. compatible = "brcm,bcm6345-uart";
  93. reg = <0xfffe0100 0x18>;
  94. interrupt-parent = <&periph_intc>;
  95. interrupts = <2>;
  96. clocks = <&periph_osc>;
  97. clock-names = "refclk";
  98. status = "disabled";
  99. };
  100. uart1: serial@fffe0120 {
  101. compatible = "brcm,bcm6345-uart";
  102. reg = <0xfffe0120 0x18>;
  103. interrupt-parent = <&periph_intc>;
  104. interrupts = <3>;
  105. clocks = <&periph_osc>;
  106. clock-names = "refclk";
  107. status = "disabled";
  108. };
  109. lsspi: spi@fffe0800 {
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. compatible = "brcm,bcm6358-spi";
  113. reg = <0xfffe0800 0x70c>;
  114. interrupt-parent = <&periph_intc>;
  115. interrupts = <1>;
  116. clocks = <&periph_clk BCM6358_CLK_SPI>;
  117. clock-names = "spi";
  118. resets = <&periph_rst BCM6358_RST_SPI>;
  119. reset-names = "spi";
  120. status = "disabled";
  121. };
  122. ehci: usb@fffe1300 {
  123. compatible = "brcm,bcm6358-ehci", "generic-ehci";
  124. reg = <0xfffe1300 0x100>;
  125. big-endian;
  126. interrupt-parent = <&periph_intc>;
  127. interrupts = <10>;
  128. phys = <&usbh 0>;
  129. phy-names = "usb";
  130. status = "disabled";
  131. };
  132. ohci: usb@fffe1400 {
  133. compatible = "brcm,bcm6358-ohci", "generic-ohci";
  134. reg = <0xfffe1400 0x100>;
  135. big-endian;
  136. no-big-frame-no;
  137. interrupt-parent = <&periph_intc>;
  138. interrupts = <5>;
  139. phys = <&usbh 0>;
  140. phy-names = "usb";
  141. status = "disabled";
  142. };
  143. usbh: usb-phy@fffe1500 {
  144. compatible = "brcm,bcm6358-usbh-phy";
  145. reg = <0xfffe1500 0x38>;
  146. #phy-cells = <1>;
  147. resets = <&periph_rst BCM6358_RST_USBH>;
  148. reset-names = "usbh";
  149. status = "disabled";
  150. };
  151. };
  152. pflash: nor@1e000000 {
  153. #address-cells = <1>;
  154. #size-cells = <1>;
  155. compatible = "cfi-flash";
  156. reg = <0x1e000000 0x2000000>;
  157. bank-width = <2>;
  158. status = "disabled";
  159. };
  160. };