bcm6328.dtsi 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include "dt-bindings/clock/bcm6328-clock.h"
  3. #include "dt-bindings/reset/bcm6328-reset.h"
  4. #include "dt-bindings/soc/bcm6328-pm.h"
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. compatible = "brcm,bcm6328";
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. mips-hpt-frequency = <160000000>;
  13. cpu@0 {
  14. compatible = "brcm,bmips4350";
  15. device_type = "cpu";
  16. reg = <0>;
  17. };
  18. cpu@1 {
  19. compatible = "brcm,bmips4350";
  20. device_type = "cpu";
  21. reg = <1>;
  22. };
  23. };
  24. clocks {
  25. periph_osc: periph-osc {
  26. compatible = "fixed-clock";
  27. #clock-cells = <0>;
  28. clock-frequency = <50000000>;
  29. clock-output-names = "periph";
  30. };
  31. hsspi_osc: hsspi-osc {
  32. compatible = "fixed-clock";
  33. #clock-cells = <0>;
  34. clock-frequency = <133333333>;
  35. clock-output-names = "hsspi_osc";
  36. };
  37. };
  38. aliases {
  39. nflash = &nflash;
  40. serial0 = &uart0;
  41. serial1 = &uart1;
  42. spi1 = &hsspi;
  43. };
  44. cpu_intc: interrupt-controller {
  45. #address-cells = <0>;
  46. compatible = "mti,cpu-interrupt-controller";
  47. interrupt-controller;
  48. #interrupt-cells = <1>;
  49. };
  50. ubus {
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. compatible = "simple-bus";
  54. ranges;
  55. periph_clk: clock-controller@10000004 {
  56. compatible = "brcm,bcm6328-clocks";
  57. reg = <0x10000004 0x4>;
  58. #clock-cells = <1>;
  59. };
  60. periph_rst: reset-controller@10000010 {
  61. compatible = "brcm,bcm6345-reset";
  62. reg = <0x10000010 0x4>;
  63. #reset-cells = <1>;
  64. };
  65. periph_intc: interrupt-controller@10000020 {
  66. compatible = "brcm,bcm6345-l1-intc";
  67. reg = <0x10000020 0x10>,
  68. <0x10000030 0x10>;
  69. interrupt-controller;
  70. #interrupt-cells = <1>;
  71. interrupt-parent = <&cpu_intc>;
  72. interrupts = <2>, <3>;
  73. };
  74. wdt: watchdog@1000005c {
  75. compatible = "brcm,bcm7038-wdt";
  76. reg = <0x1000005c 0xc>;
  77. clocks = <&periph_osc>;
  78. clock-names = "refclk";
  79. timeout-sec = <30>;
  80. };
  81. soft_reset: syscon@10000068 {
  82. compatible = "syscon";
  83. reg = <0x10000068 0x4>;
  84. native-endian;
  85. reboot {
  86. compatible = "syscon-reboot";
  87. offset = <0x0>;
  88. mask = <0x1>;
  89. };
  90. };
  91. uart0: serial@10000100 {
  92. compatible = "brcm,bcm6345-uart";
  93. reg = <0x10000100 0x18>;
  94. interrupt-parent = <&periph_intc>;
  95. interrupts = <28>;
  96. clocks = <&periph_osc>;
  97. clock-names = "refclk";
  98. status = "disabled";
  99. };
  100. uart1: serial@10000120 {
  101. compatible = "brcm,bcm6345-uart";
  102. reg = <0x10000120 0x18>;
  103. interrupt-parent = <&periph_intc>;
  104. interrupts = <39>;
  105. clocks = <&periph_osc>;
  106. clock-names = "refclk";
  107. status = "disabled";
  108. };
  109. nflash: nand@10000200 {
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. compatible = "brcm,nand-bcm6368",
  113. "brcm,brcmnand-v2.2",
  114. "brcm,brcmnand";
  115. reg = <0x10000200 0x180>,
  116. <0x10000400 0x200>,
  117. <0x10000070 0x10>;
  118. reg-names = "nand",
  119. "nand-cache",
  120. "nand-int-base";
  121. interrupt-parent = <&periph_intc>;
  122. interrupts = <0>;
  123. status = "disabled";
  124. };
  125. leds0: led-controller@10000800 {
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. compatible = "brcm,bcm6328-leds";
  129. reg = <0x10000800 0x24>;
  130. status = "disabled";
  131. };
  132. hsspi: spi@10001000 {
  133. #address-cells = <1>;
  134. #size-cells = <0>;
  135. compatible = "brcm,bcm6328-hsspi";
  136. reg = <0x10001000 0x600>;
  137. interrupt-parent = <&periph_intc>;
  138. interrupts = <29>;
  139. clocks = <&periph_clk BCM6328_CLK_HSSPI>,
  140. <&hsspi_osc>;
  141. clock-names = "hsspi",
  142. "pll";
  143. resets = <&periph_rst BCM6328_RST_SPI>;
  144. reset-names = "hsspi";
  145. status = "disabled";
  146. };
  147. periph_pwr: power-controller@10001848 {
  148. compatible = "brcm,bcm6328-power-controller";
  149. reg = <0x10001848 0x4>;
  150. #power-domain-cells = <1>;
  151. };
  152. ehci: usb@10002500 {
  153. compatible = "brcm,bcm6328-ehci", "generic-ehci";
  154. reg = <0x10002500 0x100>;
  155. big-endian;
  156. interrupt-parent = <&periph_intc>;
  157. interrupts = <42>;
  158. phys = <&usbh 0>;
  159. phy-names = "usb";
  160. status = "disabled";
  161. };
  162. ohci: usb@10002600 {
  163. compatible = "brcm,bcm6328-ohci", "generic-ohci";
  164. reg = <0x10002600 0x100>;
  165. big-endian;
  166. no-big-frame-no;
  167. interrupt-parent = <&periph_intc>;
  168. interrupts = <41>;
  169. phys = <&usbh 0>;
  170. phy-names = "usb";
  171. status = "disabled";
  172. };
  173. usbh: usb-phy@10002700 {
  174. compatible = "brcm,bcm6328-usbh-phy";
  175. reg = <0x10002700 0x38>;
  176. #phy-cells = <1>;
  177. clocks = <&periph_clk BCM6328_CLK_USBH>;
  178. clock-names = "usbh";
  179. power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_USBH>;
  180. resets = <&periph_rst BCM6328_RST_USBH>;
  181. reset-names = "usbh";
  182. status = "disabled";
  183. };
  184. };
  185. };