ar2315.c 9.3 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
  7. * Copyright (C) 2006 FON Technology, SL.
  8. * Copyright (C) 2006 Imre Kaloz <[email protected]>
  9. * Copyright (C) 2006 Felix Fietkau <[email protected]>
  10. * Copyright (C) 2012 Alexandros C. Couloumbis <[email protected]>
  11. */
  12. /*
  13. * Platform devices for Atheros AR2315 SoCs
  14. */
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <linux/bitops.h>
  18. #include <linux/irqdomain.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/memblock.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/reboot.h>
  23. #include <asm/bootinfo.h>
  24. #include <asm/reboot.h>
  25. #include <asm/time.h>
  26. #include <ath25_platform.h>
  27. #include "devices.h"
  28. #include "ar2315.h"
  29. #include "ar2315_regs.h"
  30. static void __iomem *ar2315_rst_base;
  31. static struct irq_domain *ar2315_misc_irq_domain;
  32. static inline u32 ar2315_rst_reg_read(u32 reg)
  33. {
  34. return __raw_readl(ar2315_rst_base + reg);
  35. }
  36. static inline void ar2315_rst_reg_write(u32 reg, u32 val)
  37. {
  38. __raw_writel(val, ar2315_rst_base + reg);
  39. }
  40. static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
  41. {
  42. u32 ret = ar2315_rst_reg_read(reg);
  43. ret &= ~mask;
  44. ret |= val;
  45. ar2315_rst_reg_write(reg, ret);
  46. }
  47. static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
  48. {
  49. ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
  50. ar2315_rst_reg_read(AR2315_AHB_ERR1);
  51. pr_emerg("AHB fatal error\n");
  52. machine_restart("AHB error"); /* Catastrophic failure */
  53. return IRQ_HANDLED;
  54. }
  55. static void ar2315_misc_irq_handler(struct irq_desc *desc)
  56. {
  57. u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
  58. ar2315_rst_reg_read(AR2315_IMR);
  59. unsigned nr;
  60. int ret = 0;
  61. if (pending) {
  62. struct irq_domain *domain = irq_desc_get_handler_data(desc);
  63. nr = __ffs(pending);
  64. if (nr == AR2315_MISC_IRQ_GPIO)
  65. ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
  66. else if (nr == AR2315_MISC_IRQ_WATCHDOG)
  67. ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
  68. ret = generic_handle_domain_irq(domain, nr);
  69. }
  70. if (!pending || ret)
  71. spurious_interrupt();
  72. }
  73. static void ar2315_misc_irq_unmask(struct irq_data *d)
  74. {
  75. ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
  76. }
  77. static void ar2315_misc_irq_mask(struct irq_data *d)
  78. {
  79. ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
  80. }
  81. static struct irq_chip ar2315_misc_irq_chip = {
  82. .name = "ar2315-misc",
  83. .irq_unmask = ar2315_misc_irq_unmask,
  84. .irq_mask = ar2315_misc_irq_mask,
  85. };
  86. static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
  87. irq_hw_number_t hw)
  88. {
  89. irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
  90. return 0;
  91. }
  92. static const struct irq_domain_ops ar2315_misc_irq_domain_ops = {
  93. .map = ar2315_misc_irq_map,
  94. };
  95. /*
  96. * Called when an interrupt is received, this function
  97. * determines exactly which interrupt it was, and it
  98. * invokes the appropriate handler.
  99. *
  100. * Implicitly, we also define interrupt priority by
  101. * choosing which to dispatch first.
  102. */
  103. static void ar2315_irq_dispatch(void)
  104. {
  105. u32 pending = read_c0_status() & read_c0_cause();
  106. if (pending & CAUSEF_IP3)
  107. do_IRQ(AR2315_IRQ_WLAN0);
  108. #ifdef CONFIG_PCI_AR2315
  109. else if (pending & CAUSEF_IP5)
  110. do_IRQ(AR2315_IRQ_LCBUS_PCI);
  111. #endif
  112. else if (pending & CAUSEF_IP2)
  113. do_IRQ(AR2315_IRQ_MISC);
  114. else if (pending & CAUSEF_IP7)
  115. do_IRQ(ATH25_IRQ_CPU_CLOCK);
  116. else
  117. spurious_interrupt();
  118. }
  119. void __init ar2315_arch_init_irq(void)
  120. {
  121. struct irq_domain *domain;
  122. unsigned irq;
  123. ath25_irq_dispatch = ar2315_irq_dispatch;
  124. domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
  125. &ar2315_misc_irq_domain_ops, NULL);
  126. if (!domain)
  127. panic("Failed to add IRQ domain");
  128. irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
  129. if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error",
  130. NULL))
  131. pr_err("Failed to register ar2315-ahb-error interrupt\n");
  132. irq_set_chained_handler_and_data(AR2315_IRQ_MISC,
  133. ar2315_misc_irq_handler, domain);
  134. ar2315_misc_irq_domain = domain;
  135. }
  136. void __init ar2315_init_devices(void)
  137. {
  138. /* Find board configuration */
  139. ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
  140. ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
  141. }
  142. static void ar2315_restart(char *command)
  143. {
  144. void (*mips_reset_vec)(void) = (void *)0xbfc00000;
  145. local_irq_disable();
  146. /* try reset the system via reset control */
  147. ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
  148. /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
  149. * a workaround. Give it some time to attempt a gpio based hardware
  150. * reset (atheros reference design workaround) */
  151. /* TODO: implement the GPIO reset workaround */
  152. /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
  153. * workaround. Attempt to jump to the mips reset location -
  154. * the boot loader itself might be able to recover the system */
  155. mips_reset_vec();
  156. }
  157. /*
  158. * This table is indexed by bits 5..4 of the CLOCKCTL1 register
  159. * to determine the predevisor value.
  160. */
  161. static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
  162. static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
  163. static unsigned __init ar2315_sys_clk(u32 clock_ctl)
  164. {
  165. unsigned int pllc_ctrl, cpu_div;
  166. unsigned int pllc_out, refdiv, fdiv, divby2;
  167. unsigned int clk_div;
  168. pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
  169. refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
  170. refdiv = clockctl1_predivide_table[refdiv];
  171. fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
  172. divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
  173. pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
  174. /* clkm input selected */
  175. switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
  176. case 0:
  177. case 1:
  178. clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
  179. clk_div = pllc_divide_table[clk_div];
  180. break;
  181. case 2:
  182. clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
  183. clk_div = pllc_divide_table[clk_div];
  184. break;
  185. default:
  186. pllc_out = 40000000;
  187. clk_div = 1;
  188. break;
  189. }
  190. cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
  191. cpu_div = cpu_div * 2 ?: 1;
  192. return pllc_out / (clk_div * cpu_div);
  193. }
  194. static inline unsigned ar2315_cpu_frequency(void)
  195. {
  196. return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
  197. }
  198. static inline unsigned ar2315_apb_frequency(void)
  199. {
  200. return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
  201. }
  202. void __init ar2315_plat_time_init(void)
  203. {
  204. mips_hpt_frequency = ar2315_cpu_frequency() / 2;
  205. }
  206. void __init ar2315_plat_mem_setup(void)
  207. {
  208. void __iomem *sdram_base;
  209. u32 memsize, memcfg;
  210. u32 devid;
  211. u32 config;
  212. /* Detect memory size */
  213. sdram_base = ioremap(AR2315_SDRAMCTL_BASE,
  214. AR2315_SDRAMCTL_SIZE);
  215. memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
  216. memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
  217. memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
  218. memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
  219. memsize <<= 3;
  220. memblock_add(0, memsize);
  221. iounmap(sdram_base);
  222. ar2315_rst_base = ioremap(AR2315_RST_BASE, AR2315_RST_SIZE);
  223. /* Detect the hardware based on the device ID */
  224. devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
  225. switch (devid) {
  226. case 0x91: /* Need to check */
  227. ath25_soc = ATH25_SOC_AR2318;
  228. break;
  229. case 0x90:
  230. ath25_soc = ATH25_SOC_AR2317;
  231. break;
  232. case 0x87:
  233. ath25_soc = ATH25_SOC_AR2316;
  234. break;
  235. case 0x86:
  236. default:
  237. ath25_soc = ATH25_SOC_AR2315;
  238. break;
  239. }
  240. ath25_board.devid = devid;
  241. /* Clear any lingering AHB errors */
  242. config = read_c0_config();
  243. write_c0_config(config & ~0x3);
  244. ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
  245. ar2315_rst_reg_read(AR2315_AHB_ERR1);
  246. ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
  247. _machine_restart = ar2315_restart;
  248. }
  249. #ifdef CONFIG_PCI_AR2315
  250. static struct resource ar2315_pci_res[] = {
  251. {
  252. .name = "ar2315-pci-ctrl",
  253. .flags = IORESOURCE_MEM,
  254. .start = AR2315_PCI_BASE,
  255. .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
  256. },
  257. {
  258. .name = "ar2315-pci-ext",
  259. .flags = IORESOURCE_MEM,
  260. .start = AR2315_PCI_EXT_BASE,
  261. .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
  262. },
  263. {
  264. .name = "ar2315-pci",
  265. .flags = IORESOURCE_IRQ,
  266. .start = AR2315_IRQ_LCBUS_PCI,
  267. .end = AR2315_IRQ_LCBUS_PCI,
  268. },
  269. };
  270. #endif
  271. void __init ar2315_arch_init(void)
  272. {
  273. unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
  274. AR2315_MISC_IRQ_UART0);
  275. ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
  276. #ifdef CONFIG_PCI_AR2315
  277. if (ath25_soc == ATH25_SOC_AR2315) {
  278. /* Reset PCI DMA logic */
  279. ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
  280. msleep(20);
  281. ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
  282. msleep(20);
  283. /* Configure endians */
  284. ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
  285. AR2315_CONFIG_PCIAHB_BRIDGE);
  286. /* Configure as PCI host with DMA */
  287. ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
  288. (AR2315_PCICLK_IN_FREQ_DIV_6 <<
  289. AR2315_PCICLK_DIV_S));
  290. ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
  291. ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
  292. AR2315_IF_MASK, AR2315_IF_PCI |
  293. AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
  294. (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
  295. AR2315_IF_PCI_CLK_SHIFT));
  296. platform_device_register_simple("ar2315-pci", -1,
  297. ar2315_pci_res,
  298. ARRAY_SIZE(ar2315_pci_res));
  299. }
  300. #endif
  301. }