cpuinfo.c 3.2 KB

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  1. /*
  2. * Copyright (C) 2007-2009 Michal Simek <[email protected]>
  3. * Copyright (C) 2007-2009 PetaLogix
  4. * Copyright (C) 2007 John Williams <[email protected]>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/init.h>
  12. #include <asm/cpuinfo.h>
  13. #include <asm/pvr.h>
  14. const struct cpu_ver_key cpu_ver_lookup[] = {
  15. /* These key value are as per MBV field in PVR0 */
  16. {"5.00.a", 0x01},
  17. {"5.00.b", 0x02},
  18. {"5.00.c", 0x03},
  19. {"6.00.a", 0x04},
  20. {"6.00.b", 0x06},
  21. {"7.00.a", 0x05},
  22. {"7.00.b", 0x07},
  23. {"7.10.a", 0x08},
  24. {"7.10.b", 0x09},
  25. {"7.10.c", 0x0a},
  26. {"7.10.d", 0x0b},
  27. {"7.20.a", 0x0c},
  28. {"7.20.b", 0x0d},
  29. {"7.20.c", 0x0e},
  30. {"7.20.d", 0x0f},
  31. {"7.30.a", 0x10},
  32. {"7.30.b", 0x11},
  33. {"8.00.a", 0x12},
  34. {"8.00.b", 0x13},
  35. {"8.10.a", 0x14},
  36. {"8.20.a", 0x15},
  37. {"8.20.b", 0x16},
  38. {"8.30.a", 0x17},
  39. {"8.40.a", 0x18},
  40. {"8.40.b", 0x19},
  41. {"8.50.a", 0x1a},
  42. {"8.50.b", 0x1c},
  43. {"8.50.c", 0x1e},
  44. {"9.0", 0x1b},
  45. {"9.1", 0x1d},
  46. {"9.2", 0x1f},
  47. {"9.3", 0x20},
  48. {"9.4", 0x21},
  49. {"9.5", 0x22},
  50. {"9.6", 0x23},
  51. {"10.0", 0x24},
  52. {"11.0", 0x25},
  53. {NULL, 0},
  54. };
  55. /*
  56. * FIXME Not sure if the actual key is defined by Xilinx in the PVR
  57. */
  58. const struct family_string_key family_string_lookup[] = {
  59. {"virtex2", 0x4},
  60. {"virtex2pro", 0x5},
  61. {"spartan3", 0x6},
  62. {"virtex4", 0x7},
  63. {"virtex5", 0x8},
  64. {"spartan3e", 0x9},
  65. {"spartan3a", 0xa},
  66. {"spartan3an", 0xb},
  67. {"spartan3adsp", 0xc},
  68. {"spartan6", 0xd},
  69. {"virtex6", 0xe},
  70. {"virtex7", 0xf},
  71. /* FIXME There is no key code defined for spartan2 */
  72. {"spartan2", 0xf0},
  73. {"kintex7", 0x10},
  74. {"artix7", 0x11},
  75. {"zynq7000", 0x12},
  76. {"UltraScale Virtex", 0x13},
  77. {"UltraScale Kintex", 0x14},
  78. {"UltraScale+ Zynq", 0x15},
  79. {"UltraScale+ Virtex", 0x16},
  80. {"UltraScale+ Kintex", 0x17},
  81. {"Spartan7", 0x18},
  82. {NULL, 0},
  83. };
  84. struct cpuinfo cpuinfo;
  85. static struct device_node *cpu;
  86. void __init setup_cpuinfo(void)
  87. {
  88. cpu = of_get_cpu_node(0, NULL);
  89. if (!cpu)
  90. pr_err("You don't have cpu or are missing cpu reg property!!!\n");
  91. pr_info("%s: initialising\n", __func__);
  92. switch (cpu_has_pvr()) {
  93. case 0:
  94. pr_warn("%s: No PVR support. Using static CPU info from FDT\n",
  95. __func__);
  96. set_cpuinfo_static(&cpuinfo, cpu);
  97. break;
  98. /* FIXME I found weird behavior with MB 7.00.a/b 7.10.a
  99. * please do not use FULL PVR with MMU */
  100. case 1:
  101. pr_info("%s: Using full CPU PVR support\n",
  102. __func__);
  103. set_cpuinfo_static(&cpuinfo, cpu);
  104. set_cpuinfo_pvr_full(&cpuinfo, cpu);
  105. break;
  106. default:
  107. pr_warn("%s: Unsupported PVR setting\n", __func__);
  108. set_cpuinfo_static(&cpuinfo, cpu);
  109. }
  110. if (cpuinfo.mmu_privins)
  111. pr_warn("%s: Stream instructions enabled"
  112. " - USERSPACE CAN LOCK THIS KERNEL!\n", __func__);
  113. of_node_put(cpu);
  114. }
  115. void __init setup_cpuinfo_clk(void)
  116. {
  117. struct clk *clk;
  118. clk = of_clk_get(cpu, 0);
  119. if (IS_ERR(clk)) {
  120. pr_err("ERROR: CPU CCF input clock not found\n");
  121. /* take timebase-frequency from DTS */
  122. cpuinfo.cpu_clock_freq = fcpu(cpu, "timebase-frequency");
  123. } else {
  124. cpuinfo.cpu_clock_freq = clk_get_rate(clk);
  125. }
  126. if (!cpuinfo.cpu_clock_freq) {
  127. pr_err("ERROR: CPU clock frequency not setup\n");
  128. BUG();
  129. }
  130. }