addrspace.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  4. *
  5. * Derived from MIPS:
  6. * Copyright (C) 1996, 99 Ralf Baechle
  7. * Copyright (C) 2000, 2002 Maciej W. Rozycki
  8. * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
  9. */
  10. #ifndef _ASM_ADDRSPACE_H
  11. #define _ASM_ADDRSPACE_H
  12. #include <linux/const.h>
  13. #include <asm/loongarch.h>
  14. /*
  15. * This gives the physical RAM offset.
  16. */
  17. #ifndef __ASSEMBLY__
  18. #ifndef PHYS_OFFSET
  19. #define PHYS_OFFSET _AC(0, UL)
  20. #endif
  21. extern unsigned long vm_map_base;
  22. #endif /* __ASSEMBLY__ */
  23. #ifndef IO_BASE
  24. #define IO_BASE CSR_DMW0_BASE
  25. #endif
  26. #ifndef CACHE_BASE
  27. #define CACHE_BASE CSR_DMW1_BASE
  28. #endif
  29. #ifndef UNCACHE_BASE
  30. #define UNCACHE_BASE CSR_DMW0_BASE
  31. #endif
  32. #define DMW_PABITS 48
  33. #define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1)
  34. /*
  35. * Memory above this physical address will be considered highmem.
  36. */
  37. #ifndef HIGHMEM_START
  38. #define HIGHMEM_START (_AC(1, UL) << _AC(DMW_PABITS, UL))
  39. #endif
  40. #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
  41. #define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK))
  42. #define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK))
  43. /*
  44. * This handles the memory map.
  45. */
  46. #ifndef PAGE_OFFSET
  47. #define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET)
  48. #endif
  49. #ifndef FIXADDR_TOP
  50. #define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
  51. #endif
  52. #ifdef __ASSEMBLY__
  53. #define _ATYPE_
  54. #define _ATYPE32_
  55. #define _ATYPE64_
  56. #define _CONST64_(x) x
  57. #else
  58. #define _ATYPE_ __PTRDIFF_TYPE__
  59. #define _ATYPE32_ int
  60. #define _ATYPE64_ __s64
  61. #ifdef CONFIG_64BIT
  62. #define _CONST64_(x) x ## L
  63. #else
  64. #define _CONST64_(x) x ## LL
  65. #endif
  66. #endif
  67. /*
  68. * 32/64-bit LoongArch address spaces
  69. */
  70. #ifdef __ASSEMBLY__
  71. #define _ACAST32_
  72. #define _ACAST64_
  73. #else
  74. #define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
  75. #define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
  76. #endif
  77. #ifdef CONFIG_32BIT
  78. #define UVRANGE 0x00000000
  79. #define KPRANGE0 0x80000000
  80. #define KPRANGE1 0xa0000000
  81. #define KVRANGE 0xc0000000
  82. #else
  83. #define XUVRANGE _CONST64_(0x0000000000000000)
  84. #define XSPRANGE _CONST64_(0x4000000000000000)
  85. #define XKPRANGE _CONST64_(0x8000000000000000)
  86. #define XKVRANGE _CONST64_(0xc000000000000000)
  87. #endif
  88. /*
  89. * Returns the physical address of a KPRANGEx / XKPRANGE address
  90. */
  91. #define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
  92. /*
  93. * On LoongArch, I/O ports mappring is following:
  94. *
  95. * | .... |
  96. * |-----------------------|
  97. * | pci io ports(16K~32M) |
  98. * |-----------------------|
  99. * | isa io ports(0 ~16K) |
  100. * PCI_IOBASE ->|-----------------------|
  101. * | .... |
  102. */
  103. #define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
  104. #define PCI_IOSIZE SZ_32M
  105. #define ISA_IOSIZE SZ_16K
  106. #define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
  107. #endif /* _ASM_ADDRSPACE_H */