sys_regs.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2012,2013 - ARM Ltd
  4. * Author: Marc Zyngier <[email protected]>
  5. *
  6. * Derived from arch/arm/kvm/coproc.h
  7. * Copyright (C) 2012 - Virtual Open Systems and Columbia University
  8. * Authors: Christoffer Dall <[email protected]>
  9. */
  10. #ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__
  11. #define __ARM64_KVM_SYS_REGS_LOCAL_H__
  12. #include <linux/bsearch.h>
  13. #define reg_to_encoding(x) \
  14. sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
  15. (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
  16. struct sys_reg_params {
  17. u8 Op0;
  18. u8 Op1;
  19. u8 CRn;
  20. u8 CRm;
  21. u8 Op2;
  22. u64 regval;
  23. bool is_write;
  24. };
  25. #define esr_sys64_to_params(esr) \
  26. ((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3, \
  27. .Op1 = ((esr) >> 14) & 0x7, \
  28. .CRn = ((esr) >> 10) & 0xf, \
  29. .CRm = ((esr) >> 1) & 0xf, \
  30. .Op2 = ((esr) >> 17) & 0x7, \
  31. .is_write = !((esr) & 1) })
  32. #define esr_cp1x_32_to_params(esr) \
  33. ((struct sys_reg_params){ .Op1 = ((esr) >> 14) & 0x7, \
  34. .CRn = ((esr) >> 10) & 0xf, \
  35. .CRm = ((esr) >> 1) & 0xf, \
  36. .Op2 = ((esr) >> 17) & 0x7, \
  37. .is_write = !((esr) & 1) })
  38. struct sys_reg_desc {
  39. /* Sysreg string for debug */
  40. const char *name;
  41. enum {
  42. AA32_DIRECT,
  43. AA32_LO,
  44. AA32_HI,
  45. } aarch32_map;
  46. /* MRS/MSR instruction which accesses it. */
  47. u8 Op0;
  48. u8 Op1;
  49. u8 CRn;
  50. u8 CRm;
  51. u8 Op2;
  52. /* Trapped access from guest, if non-NULL. */
  53. bool (*access)(struct kvm_vcpu *,
  54. struct sys_reg_params *,
  55. const struct sys_reg_desc *);
  56. /* Initialization for vcpu. */
  57. void (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
  58. /* Index into sys_reg[], or 0 if we don't need to save it. */
  59. int reg;
  60. /* Value (usually reset value) */
  61. u64 val;
  62. /* Custom get/set_user functions, fallback to generic if NULL */
  63. int (*get_user)(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
  64. u64 *val);
  65. int (*set_user)(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
  66. u64 val);
  67. /* Return mask of REG_* runtime visibility overrides */
  68. unsigned int (*visibility)(const struct kvm_vcpu *vcpu,
  69. const struct sys_reg_desc *rd);
  70. };
  71. #define REG_HIDDEN (1 << 0) /* hidden from userspace and guest */
  72. #define REG_RAZ (1 << 1) /* RAZ from userspace and guest */
  73. #define REG_USER_WI (1 << 2) /* WI from userspace only */
  74. static __printf(2, 3)
  75. inline void print_sys_reg_msg(const struct sys_reg_params *p,
  76. char *fmt, ...)
  77. {
  78. va_list va;
  79. va_start(va, fmt);
  80. /* Look, we even formatted it for you to paste into the table! */
  81. kvm_pr_unimpl("%pV { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n",
  82. &(struct va_format){ fmt, &va },
  83. p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read");
  84. va_end(va);
  85. }
  86. static inline void print_sys_reg_instr(const struct sys_reg_params *p)
  87. {
  88. /* GCC warns on an empty format string */
  89. print_sys_reg_msg(p, "%s", "");
  90. }
  91. static inline bool ignore_write(struct kvm_vcpu *vcpu,
  92. const struct sys_reg_params *p)
  93. {
  94. return true;
  95. }
  96. static inline bool read_zero(struct kvm_vcpu *vcpu,
  97. struct sys_reg_params *p)
  98. {
  99. p->regval = 0;
  100. return true;
  101. }
  102. /* Reset functions */
  103. static inline void reset_unknown(struct kvm_vcpu *vcpu,
  104. const struct sys_reg_desc *r)
  105. {
  106. BUG_ON(!r->reg);
  107. BUG_ON(r->reg >= NR_SYS_REGS);
  108. __vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
  109. }
  110. static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
  111. {
  112. BUG_ON(!r->reg);
  113. BUG_ON(r->reg >= NR_SYS_REGS);
  114. __vcpu_sys_reg(vcpu, r->reg) = r->val;
  115. }
  116. static inline unsigned int sysreg_visibility(const struct kvm_vcpu *vcpu,
  117. const struct sys_reg_desc *r)
  118. {
  119. if (likely(!r->visibility))
  120. return 0;
  121. return r->visibility(vcpu, r);
  122. }
  123. static inline bool sysreg_hidden(const struct kvm_vcpu *vcpu,
  124. const struct sys_reg_desc *r)
  125. {
  126. return sysreg_visibility(vcpu, r) & REG_HIDDEN;
  127. }
  128. static inline bool sysreg_visible_as_raz(const struct kvm_vcpu *vcpu,
  129. const struct sys_reg_desc *r)
  130. {
  131. return sysreg_visibility(vcpu, r) & REG_RAZ;
  132. }
  133. static inline bool sysreg_user_write_ignore(const struct kvm_vcpu *vcpu,
  134. const struct sys_reg_desc *r)
  135. {
  136. return sysreg_visibility(vcpu, r) & REG_USER_WI;
  137. }
  138. static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
  139. const struct sys_reg_desc *i2)
  140. {
  141. BUG_ON(i1 == i2);
  142. if (!i1)
  143. return 1;
  144. else if (!i2)
  145. return -1;
  146. if (i1->Op0 != i2->Op0)
  147. return i1->Op0 - i2->Op0;
  148. if (i1->Op1 != i2->Op1)
  149. return i1->Op1 - i2->Op1;
  150. if (i1->CRn != i2->CRn)
  151. return i1->CRn - i2->CRn;
  152. if (i1->CRm != i2->CRm)
  153. return i1->CRm - i2->CRm;
  154. return i1->Op2 - i2->Op2;
  155. }
  156. static inline int match_sys_reg(const void *key, const void *elt)
  157. {
  158. const unsigned long pval = (unsigned long)key;
  159. const struct sys_reg_desc *r = elt;
  160. return pval - reg_to_encoding(r);
  161. }
  162. static inline const struct sys_reg_desc *
  163. find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[],
  164. unsigned int num)
  165. {
  166. unsigned long pval = reg_to_encoding(params);
  167. return __inline_bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
  168. }
  169. static inline u64 calculate_mpidr(const struct kvm_vcpu *vcpu)
  170. {
  171. u64 mpidr;
  172. /*
  173. * Map the vcpu_id into the first three affinity level fields of
  174. * the MPIDR. We limit the number of VCPUs in level 0 due to a
  175. * limitation to 16 CPUs in that level in the ICC_SGIxR registers
  176. * of the GICv3 to be able to address each CPU directly when
  177. * sending IPIs.
  178. */
  179. mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
  180. mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
  181. mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
  182. mpidr |= (1ULL << 31);
  183. return mpidr;
  184. }
  185. const struct sys_reg_desc *get_reg_by_id(u64 id,
  186. const struct sys_reg_desc table[],
  187. unsigned int num);
  188. int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
  189. int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
  190. int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
  191. const struct sys_reg_desc table[], unsigned int num);
  192. int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
  193. const struct sys_reg_desc table[], unsigned int num);
  194. #define AA32(_x) .aarch32_map = AA32_##_x
  195. #define Op0(_x) .Op0 = _x
  196. #define Op1(_x) .Op1 = _x
  197. #define CRn(_x) .CRn = _x
  198. #define CRm(_x) .CRm = _x
  199. #define Op2(_x) .Op2 = _x
  200. #define SYS_DESC(reg) \
  201. .name = #reg, \
  202. Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
  203. CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \
  204. Op2(sys_reg_Op2(reg))
  205. #endif /* __ARM64_KVM_SYS_REGS_LOCAL_H__ */