cacheinfo.c 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ARM64 cacheinfo support
  4. *
  5. * Copyright (C) 2015 ARM Ltd.
  6. * All Rights Reserved
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/cacheinfo.h>
  10. #include <linux/of.h>
  11. #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
  12. /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
  13. #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
  14. #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
  15. #define CLIDR_CTYPE(clidr, level) \
  16. (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
  17. int cache_line_size(void)
  18. {
  19. if (coherency_max_size != 0)
  20. return coherency_max_size;
  21. return cache_line_size_of_cpu();
  22. }
  23. EXPORT_SYMBOL_GPL(cache_line_size);
  24. static inline enum cache_type get_cache_type(int level)
  25. {
  26. u64 clidr;
  27. if (level > MAX_CACHE_LEVEL)
  28. return CACHE_TYPE_NOCACHE;
  29. clidr = read_sysreg(clidr_el1);
  30. return CLIDR_CTYPE(clidr, level);
  31. }
  32. static void ci_leaf_init(struct cacheinfo *this_leaf,
  33. enum cache_type type, unsigned int level)
  34. {
  35. this_leaf->level = level;
  36. this_leaf->type = type;
  37. }
  38. int init_cache_level(unsigned int cpu)
  39. {
  40. unsigned int ctype, level, leaves;
  41. int fw_level;
  42. struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
  43. for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
  44. ctype = get_cache_type(level);
  45. if (ctype == CACHE_TYPE_NOCACHE) {
  46. level--;
  47. break;
  48. }
  49. /* Separate instruction and data caches */
  50. leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
  51. }
  52. if (acpi_disabled)
  53. fw_level = of_find_last_cache_level(cpu);
  54. else
  55. fw_level = acpi_find_last_cache_level(cpu);
  56. if (fw_level < 0)
  57. return fw_level;
  58. if (level < fw_level) {
  59. /*
  60. * some external caches not specified in CLIDR_EL1
  61. * the information may be available in the device tree
  62. * only unified external caches are considered here
  63. */
  64. leaves += (fw_level - level);
  65. level = fw_level;
  66. }
  67. this_cpu_ci->num_levels = level;
  68. this_cpu_ci->num_leaves = leaves;
  69. return 0;
  70. }
  71. int populate_cache_leaves(unsigned int cpu)
  72. {
  73. unsigned int level, idx;
  74. enum cache_type type;
  75. struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
  76. struct cacheinfo *this_leaf = this_cpu_ci->info_list;
  77. for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
  78. idx < this_cpu_ci->num_leaves; idx++, level++) {
  79. type = get_cache_type(level);
  80. if (type == CACHE_TYPE_SEPARATE) {
  81. ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
  82. ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
  83. } else {
  84. ci_leaf_init(this_leaf++, type, level);
  85. }
  86. }
  87. return 0;
  88. }