1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556 |
- // SPDX-License-Identifier: GPL-2.0+
- /*
- * dts file for Xilinx ZynqMP ZC1254
- *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
- *
- * Michal Simek <[email protected]>
- * Siva Durga Prasad Paladugu <[email protected]>
- */
- /dts-v1/;
- #include "zynqmp.dtsi"
- #include "zynqmp-clk-ccf.dtsi"
- / {
- model = "ZynqMP ZC1254 RevA";
- compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
- aliases {
- serial0 = &uart0;
- serial1 = &dcc;
- spi0 = &qspi;
- };
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- };
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
- };
- &dcc {
- status = "okay";
- };
- &qspi {
- status = "okay";
- flash@0 {
- compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
- spi-max-frequency = <108000000>; /* Based on DC1 spec */
- };
- };
- &uart0 {
- status = "okay";
- };
|