zynqmp-sm-k26-revA.dts 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
  4. *
  5. * (C) Copyright 2020 - 2021, Xilinx, Inc.
  6. *
  7. * Michal Simek <[email protected]>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk-ccf.dtsi"
  12. #include <dt-bindings/input/input.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. #include <dt-bindings/phy/phy.h>
  15. / {
  16. model = "ZynqMP SM-K26 Rev1/B/A";
  17. compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
  18. "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
  19. "xlnx,zynqmp";
  20. aliases {
  21. i2c0 = &i2c0;
  22. i2c1 = &i2c1;
  23. mmc0 = &sdhci0;
  24. mmc1 = &sdhci1;
  25. nvmem0 = &eeprom;
  26. nvmem1 = &eeprom_cc;
  27. rtc0 = &rtc;
  28. serial0 = &uart0;
  29. serial1 = &uart1;
  30. serial2 = &dcc;
  31. spi0 = &qspi;
  32. spi1 = &spi0;
  33. spi2 = &spi1;
  34. usb0 = &usb0;
  35. usb1 = &usb1;
  36. };
  37. chosen {
  38. bootargs = "earlycon";
  39. stdout-path = "serial1:115200n8";
  40. };
  41. memory@0 {
  42. device_type = "memory"; /* 4GB */
  43. reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44. };
  45. gpio-keys {
  46. compatible = "gpio-keys";
  47. autorepeat;
  48. key-fwuen {
  49. label = "fwuen";
  50. gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  51. };
  52. };
  53. leds {
  54. compatible = "gpio-leds";
  55. ds35-led {
  56. label = "heartbeat";
  57. gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
  58. linux,default-trigger = "heartbeat";
  59. };
  60. ds36-led {
  61. label = "vbus_det";
  62. gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
  63. default-state = "on";
  64. };
  65. };
  66. };
  67. &uart1 { /* MIO36/MIO37 */
  68. status = "okay";
  69. };
  70. &qspi { /* MIO 0-5 - U143 */
  71. status = "okay";
  72. flash@0 { /* MT25QU512A */
  73. compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
  74. #address-cells = <1>;
  75. #size-cells = <1>;
  76. reg = <0>;
  77. spi-tx-bus-width = <1>;
  78. spi-rx-bus-width = <4>;
  79. spi-max-frequency = <40000000>; /* 40MHz */
  80. partition@0 {
  81. label = "Image Selector";
  82. reg = <0x0 0x80000>; /* 512KB */
  83. read-only;
  84. lock;
  85. };
  86. partition@80000 {
  87. label = "Image Selector Golden";
  88. reg = <0x80000 0x80000>; /* 512KB */
  89. read-only;
  90. lock;
  91. };
  92. partition@100000 {
  93. label = "Persistent Register";
  94. reg = <0x100000 0x20000>; /* 128KB */
  95. };
  96. partition@120000 {
  97. label = "Persistent Register Backup";
  98. reg = <0x120000 0x20000>; /* 128KB */
  99. };
  100. partition@140000 {
  101. label = "Open_1";
  102. reg = <0x140000 0xC0000>; /* 768KB */
  103. };
  104. partition@200000 {
  105. label = "Image A (FSBL, PMU, ATF, U-Boot)";
  106. reg = <0x200000 0xD00000>; /* 13MB */
  107. };
  108. partition@f00000 {
  109. label = "ImgSel Image A Catch";
  110. reg = <0xF00000 0x80000>; /* 512KB */
  111. read-only;
  112. lock;
  113. };
  114. partition@f80000 {
  115. label = "Image B (FSBL, PMU, ATF, U-Boot)";
  116. reg = <0xF80000 0xD00000>; /* 13MB */
  117. };
  118. partition@1c80000 {
  119. label = "ImgSel Image B Catch";
  120. reg = <0x1C80000 0x80000>; /* 512KB */
  121. read-only;
  122. lock;
  123. };
  124. partition@1d00000 {
  125. label = "Open_2";
  126. reg = <0x1D00000 0x100000>; /* 1MB */
  127. };
  128. partition@1e00000 {
  129. label = "Recovery Image";
  130. reg = <0x1E00000 0x200000>; /* 2MB */
  131. read-only;
  132. lock;
  133. };
  134. partition@2000000 {
  135. label = "Recovery Image Backup";
  136. reg = <0x2000000 0x200000>; /* 2MB */
  137. read-only;
  138. lock;
  139. };
  140. partition@2200000 {
  141. label = "U-Boot storage variables";
  142. reg = <0x2200000 0x20000>; /* 128KB */
  143. };
  144. partition@2220000 {
  145. label = "U-Boot storage variables backup";
  146. reg = <0x2220000 0x20000>; /* 128KB */
  147. };
  148. partition@2240000 {
  149. label = "SHA256";
  150. reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
  151. read-only;
  152. lock;
  153. };
  154. partition@2250000 {
  155. label = "User";
  156. reg = <0x2250000 0x1db0000>; /* 29.5 MB */
  157. };
  158. };
  159. };
  160. &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
  161. status = "okay";
  162. non-removable;
  163. disable-wp;
  164. bus-width = <8>;
  165. xlnx,mio-bank = <0>;
  166. };
  167. &spi1 { /* MIO6, 9-11 */
  168. status = "okay";
  169. label = "TPM";
  170. num-cs = <1>;
  171. tpm@0 { /* slm9670 - U144 */
  172. compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
  173. reg = <0>;
  174. spi-max-frequency = <18500000>;
  175. };
  176. };
  177. &i2c1 {
  178. status = "okay";
  179. clock-frequency = <400000>;
  180. scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
  181. sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
  182. eeprom: eeprom@50 { /* u46 - also at address 0x58 */
  183. compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
  184. reg = <0x50>;
  185. /* WP pin EE_WP_EN connected to slg7x644092@68 */
  186. };
  187. eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
  188. compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
  189. reg = <0x51>;
  190. };
  191. /* da9062@30 - u170 - also at address 0x31 */
  192. /* da9131@33 - u167 */
  193. da9131: pmic@33 {
  194. compatible = "dlg,da9131";
  195. reg = <0x33>;
  196. regulators {
  197. da9131_buck1: buck1 {
  198. regulator-name = "da9131_buck1";
  199. regulator-boot-on;
  200. regulator-always-on;
  201. };
  202. da9131_buck2: buck2 {
  203. regulator-name = "da9131_buck2";
  204. regulator-boot-on;
  205. regulator-always-on;
  206. };
  207. };
  208. };
  209. /* da9130@32 - u166 */
  210. da9130: pmic@32 {
  211. compatible = "dlg,da9130";
  212. reg = <0x32>;
  213. regulators {
  214. da9130_buck1: buck1 {
  215. regulator-name = "da9130_buck1";
  216. regulator-boot-on;
  217. regulator-always-on;
  218. };
  219. };
  220. };
  221. /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
  222. /*
  223. * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
  224. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
  225. * Address conflict with slg7x644091@70 making both the devices NOT accessible.
  226. * With the FW fix, stdp4320 should respond to address 0x73 only.
  227. */
  228. /* slg7x644092@68 - u169 */
  229. /* Also connected via JA1C as C23/C24 */
  230. };
  231. &gpio {
  232. status = "okay";
  233. gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
  234. "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
  235. "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
  236. "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
  237. "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
  238. "I2C1_SDA", "", "", "", "", /* 25 - 29 */
  239. "", "", "", "", "", /* 30 - 34 */
  240. "", "", "", "", "", /* 35 - 39 */
  241. "", "", "", "", "", /* 40 - 44 */
  242. "", "", "", "", "", /* 45 - 49 */
  243. "", "", "", "", "", /* 50 - 54 */
  244. "", "", "", "", "", /* 55 - 59 */
  245. "", "", "", "", "", /* 60 - 64 */
  246. "", "", "", "", "", /* 65 - 69 */
  247. "", "", "", "", "", /* 70 - 74 */
  248. "", "", "", /* 75 - 77, MIO end and EMIO start */
  249. "", "", /* 78 - 79 */
  250. "", "", "", "", "", /* 80 - 84 */
  251. "", "", "", "", "", /* 85 - 89 */
  252. "", "", "", "", "", /* 90 - 94 */
  253. "", "", "", "", "", /* 95 - 99 */
  254. "", "", "", "", "", /* 100 - 104 */
  255. "", "", "", "", "", /* 105 - 109 */
  256. "", "", "", "", "", /* 110 - 114 */
  257. "", "", "", "", "", /* 115 - 119 */
  258. "", "", "", "", "", /* 120 - 124 */
  259. "", "", "", "", "", /* 125 - 129 */
  260. "", "", "", "", "", /* 130 - 134 */
  261. "", "", "", "", "", /* 135 - 139 */
  262. "", "", "", "", "", /* 140 - 144 */
  263. "", "", "", "", "", /* 145 - 149 */
  264. "", "", "", "", "", /* 150 - 154 */
  265. "", "", "", "", "", /* 155 - 159 */
  266. "", "", "", "", "", /* 160 - 164 */
  267. "", "", "", "", "", /* 165 - 169 */
  268. "", "", "", ""; /* 170 - 173 */
  269. };