k3-j721s2-som-p0.dtsi 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SoM: https://www.ti.com/lit/zip/sprr439
  4. *
  5. * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
  6. */
  7. /dts-v1/;
  8. #include "k3-j721s2.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. / {
  11. memory@80000000 {
  12. device_type = "memory";
  13. /* 16 GB RAM */
  14. reg = <0x00 0x80000000 0x00 0x80000000>,
  15. <0x08 0x80000000 0x03 0x80000000>;
  16. };
  17. /* Reserving memory regions still pending */
  18. reserved_memory: reserved-memory {
  19. #address-cells = <2>;
  20. #size-cells = <2>;
  21. ranges;
  22. secure_ddr: optee@9e800000 {
  23. reg = <0x00 0x9e800000 0x00 0x01800000>;
  24. alignment = <0x1000>;
  25. no-map;
  26. };
  27. };
  28. transceiver0: can-phy0 {
  29. /* standby pin has been grounded by default */
  30. compatible = "ti,tcan1042";
  31. #phy-cells = <0>;
  32. max-bitrate = <5000000>;
  33. };
  34. };
  35. &main_pmx0 {
  36. main_i2c0_pins_default: main-i2c0-pins-default {
  37. pinctrl-single,pins = <
  38. J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
  39. J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
  40. >;
  41. };
  42. main_mcan16_pins_default: main-mcan16-pins-default {
  43. pinctrl-single,pins = <
  44. J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
  45. J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
  46. >;
  47. };
  48. };
  49. &main_i2c0 {
  50. pinctrl-names = "default";
  51. pinctrl-0 = <&main_i2c0_pins_default>;
  52. clock-frequency = <400000>;
  53. exp_som: gpio@21 {
  54. compatible = "ti,tca6408";
  55. reg = <0x21>;
  56. gpio-controller;
  57. #gpio-cells = <2>;
  58. gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
  59. "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
  60. "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
  61. "GPIO_LIN_EN", "CAN_STB";
  62. };
  63. };
  64. &main_mcan16 {
  65. pinctrl-0 = <&main_mcan16_pins_default>;
  66. pinctrl-names = "default";
  67. phys = <&transceiver0>;
  68. };
  69. &mailbox0_cluster0 {
  70. status = "disabled";
  71. };
  72. &mailbox0_cluster1 {
  73. status = "disabled";
  74. };
  75. &mailbox0_cluster2 {
  76. status = "disabled";
  77. };
  78. &mailbox0_cluster3 {
  79. status = "disabled";
  80. };
  81. &mailbox0_cluster4 {
  82. status = "disabled";
  83. };
  84. &mailbox0_cluster5 {
  85. status = "disabled";
  86. };
  87. &mailbox0_cluster6 {
  88. status = "disabled";
  89. };
  90. &mailbox0_cluster7 {
  91. status = "disabled";
  92. };
  93. &mailbox0_cluster8 {
  94. status = "disabled";
  95. };
  96. &mailbox0_cluster9 {
  97. status = "disabled";
  98. };
  99. &mailbox0_cluster10 {
  100. status = "disabled";
  101. };
  102. &mailbox0_cluster11 {
  103. status = "disabled";
  104. };
  105. &mailbox1_cluster0 {
  106. status = "disabled";
  107. };
  108. &mailbox1_cluster1 {
  109. status = "disabled";
  110. };
  111. &mailbox1_cluster2 {
  112. status = "disabled";
  113. };
  114. &mailbox1_cluster3 {
  115. status = "disabled";
  116. };
  117. &mailbox1_cluster4 {
  118. status = "disabled";
  119. };
  120. &mailbox1_cluster5 {
  121. status = "disabled";
  122. };
  123. &mailbox1_cluster6 {
  124. status = "disabled";
  125. };
  126. &mailbox1_cluster7 {
  127. status = "disabled";
  128. };
  129. &mailbox1_cluster8 {
  130. status = "disabled";
  131. };
  132. &mailbox1_cluster9 {
  133. status = "disabled";
  134. };
  135. &mailbox1_cluster10 {
  136. status = "disabled";
  137. };
  138. &mailbox1_cluster11 {
  139. status = "disabled";
  140. };