k3-am654-base-board.dts 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
  4. */
  5. /dts-v1/;
  6. #include "k3-am654.dtsi"
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/net/ti-dp83867.h>
  9. / {
  10. compatible = "ti,am654-evm", "ti,am654";
  11. model = "Texas Instruments AM654 Base Board";
  12. chosen {
  13. stdout-path = "serial2:115200n8";
  14. bootargs = "earlycon=ns16550a,mmio32,0x02800000";
  15. };
  16. memory@80000000 {
  17. device_type = "memory";
  18. /* 4G RAM */
  19. reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
  20. <0x00000008 0x80000000 0x00000000 0x80000000>;
  21. };
  22. reserved-memory {
  23. #address-cells = <2>;
  24. #size-cells = <2>;
  25. ranges;
  26. secure_ddr: secure-ddr@9e800000 {
  27. reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
  28. alignment = <0x1000>;
  29. no-map;
  30. };
  31. mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
  32. compatible = "shared-dma-pool";
  33. reg = <0 0xa0000000 0 0x100000>;
  34. no-map;
  35. };
  36. mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
  37. compatible = "shared-dma-pool";
  38. reg = <0 0xa0100000 0 0xf00000>;
  39. no-map;
  40. };
  41. mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
  42. compatible = "shared-dma-pool";
  43. reg = <0 0xa1000000 0 0x100000>;
  44. no-map;
  45. };
  46. mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
  47. compatible = "shared-dma-pool";
  48. reg = <0 0xa1100000 0 0xf00000>;
  49. no-map;
  50. };
  51. rtos_ipc_memory_region: ipc-memories@a2000000 {
  52. reg = <0x00 0xa2000000 0x00 0x00100000>;
  53. alignment = <0x1000>;
  54. no-map;
  55. };
  56. };
  57. gpio-keys {
  58. compatible = "gpio-keys";
  59. autorepeat;
  60. pinctrl-names = "default";
  61. pinctrl-0 = <&push_button_pins_default>;
  62. switch-5 {
  63. label = "GPIO Key USER1";
  64. linux,code = <BTN_0>;
  65. gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
  66. };
  67. switch-6 {
  68. label = "GPIO Key USER2";
  69. linux,code = <BTN_1>;
  70. gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
  71. };
  72. };
  73. evm_12v0: fixedregulator-evm12v0 {
  74. /* main supply */
  75. compatible = "regulator-fixed";
  76. regulator-name = "evm_12v0";
  77. regulator-min-microvolt = <12000000>;
  78. regulator-max-microvolt = <12000000>;
  79. regulator-always-on;
  80. regulator-boot-on;
  81. };
  82. vcc3v3_io: fixedregulator-vcc3v3io {
  83. /* Output of TPS54334 */
  84. compatible = "regulator-fixed";
  85. regulator-name = "vcc3v3_io";
  86. regulator-min-microvolt = <3300000>;
  87. regulator-max-microvolt = <3300000>;
  88. regulator-always-on;
  89. regulator-boot-on;
  90. vin-supply = <&evm_12v0>;
  91. };
  92. vdd_mmc1_sd: fixedregulator-sd {
  93. compatible = "regulator-fixed";
  94. regulator-name = "vdd_mmc1_sd";
  95. regulator-min-microvolt = <3300000>;
  96. regulator-max-microvolt = <3300000>;
  97. regulator-boot-on;
  98. enable-active-high;
  99. vin-supply = <&vcc3v3_io>;
  100. gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
  101. };
  102. };
  103. &wkup_pmx0 {
  104. wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  105. pinctrl-single,pins = <
  106. AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
  107. AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
  108. >;
  109. };
  110. push_button_pins_default: push-button-pins-default {
  111. pinctrl-single,pins = <
  112. AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
  113. AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
  114. >;
  115. };
  116. mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
  117. pinctrl-single,pins = <
  118. AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
  119. AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
  120. AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
  121. AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
  122. AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
  123. AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
  124. AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
  125. AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
  126. AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
  127. AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
  128. AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
  129. >;
  130. };
  131. wkup_pca554_default: wkup-pca554-default {
  132. pinctrl-single,pins = <
  133. AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
  134. >;
  135. };
  136. mcu_cpsw_pins_default: mcu-cpsw-pins-default {
  137. pinctrl-single,pins = <
  138. AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
  139. AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
  140. AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
  141. AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
  142. AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
  143. AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
  144. AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
  145. AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
  146. AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
  147. AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
  148. AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
  149. AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
  150. >;
  151. };
  152. mcu_mdio_pins_default: mcu-mdio1-pins-default {
  153. pinctrl-single,pins = <
  154. AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  155. AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  156. >;
  157. };
  158. };
  159. &main_pmx0 {
  160. main_uart0_pins_default: main-uart0-pins-default {
  161. pinctrl-single,pins = <
  162. AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
  163. AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
  164. AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
  165. AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
  166. >;
  167. };
  168. main_i2c2_pins_default: main-i2c2-pins-default {
  169. pinctrl-single,pins = <
  170. AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
  171. AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
  172. >;
  173. };
  174. main_spi0_pins_default: main-spi0-pins-default {
  175. pinctrl-single,pins = <
  176. AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
  177. AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
  178. AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
  179. AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
  180. >;
  181. };
  182. main_mmc0_pins_default: main-mmc0-pins-default {
  183. pinctrl-single,pins = <
  184. AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
  185. AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
  186. AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
  187. AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
  188. AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
  189. AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
  190. AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
  191. AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
  192. AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
  193. AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
  194. AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
  195. AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
  196. >;
  197. };
  198. main_mmc1_pins_default: main-mmc1-pins-default {
  199. pinctrl-single,pins = <
  200. AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
  201. AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
  202. AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
  203. AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
  204. AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
  205. AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
  206. AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
  207. AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
  208. >;
  209. };
  210. usb1_pins_default: usb1-pins-default {
  211. pinctrl-single,pins = <
  212. AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
  213. >;
  214. };
  215. };
  216. &main_pmx1 {
  217. main_i2c0_pins_default: main-i2c0-pins-default {
  218. pinctrl-single,pins = <
  219. AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
  220. AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
  221. >;
  222. };
  223. main_i2c1_pins_default: main-i2c1-pins-default {
  224. pinctrl-single,pins = <
  225. AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
  226. AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
  227. >;
  228. };
  229. ecap0_pins_default: ecap0-pins-default {
  230. pinctrl-single,pins = <
  231. AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
  232. >;
  233. };
  234. };
  235. &wkup_uart0 {
  236. /* Wakeup UART is used by System firmware */
  237. status = "reserved";
  238. };
  239. &main_uart0 {
  240. pinctrl-names = "default";
  241. pinctrl-0 = <&main_uart0_pins_default>;
  242. power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
  243. };
  244. &wkup_i2c0 {
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&wkup_i2c0_pins_default>;
  247. clock-frequency = <400000>;
  248. pca9554: gpio@39 {
  249. compatible = "nxp,pca9554";
  250. reg = <0x39>;
  251. gpio-controller;
  252. #gpio-cells = <2>;
  253. pinctrl-names = "default";
  254. pinctrl-0 = <&wkup_pca554_default>;
  255. interrupt-parent = <&wkup_gpio0>;
  256. interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
  257. interrupt-controller;
  258. #interrupt-cells = <2>;
  259. };
  260. };
  261. &main_i2c0 {
  262. pinctrl-names = "default";
  263. pinctrl-0 = <&main_i2c0_pins_default>;
  264. clock-frequency = <400000>;
  265. pca9555: gpio@21 {
  266. compatible = "nxp,pca9555";
  267. reg = <0x21>;
  268. gpio-controller;
  269. #gpio-cells = <2>;
  270. };
  271. };
  272. &main_i2c1 {
  273. pinctrl-names = "default";
  274. pinctrl-0 = <&main_i2c1_pins_default>;
  275. clock-frequency = <400000>;
  276. };
  277. &main_i2c2 {
  278. pinctrl-names = "default";
  279. pinctrl-0 = <&main_i2c2_pins_default>;
  280. clock-frequency = <400000>;
  281. };
  282. &ecap0 {
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&ecap0_pins_default>;
  285. };
  286. &main_spi0 {
  287. pinctrl-names = "default";
  288. pinctrl-0 = <&main_spi0_pins_default>;
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. ti,pindir-d0-out-d1-in;
  292. flash@0 {
  293. compatible = "jedec,spi-nor";
  294. reg = <0x0>;
  295. spi-tx-bus-width = <1>;
  296. spi-rx-bus-width = <1>;
  297. spi-max-frequency = <48000000>;
  298. };
  299. };
  300. &sdhci0 {
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&main_mmc0_pins_default>;
  303. bus-width = <8>;
  304. non-removable;
  305. ti,driver-strength-ohm = <50>;
  306. disable-wp;
  307. };
  308. /*
  309. * Because of erratas i2025 and i2026 for silicon revision 1.0, the
  310. * SD card interface might fail. Boards with sr1.0 are recommended to
  311. * disable sdhci1
  312. */
  313. &sdhci1 {
  314. vmmc-supply = <&vdd_mmc1_sd>;
  315. pinctrl-names = "default";
  316. pinctrl-0 = <&main_mmc1_pins_default>;
  317. ti,driver-strength-ohm = <50>;
  318. disable-wp;
  319. };
  320. &usb1 {
  321. pinctrl-names = "default";
  322. pinctrl-0 = <&usb1_pins_default>;
  323. dr_mode = "otg";
  324. };
  325. &dwc3_0 {
  326. status = "disabled";
  327. };
  328. &usb0_phy {
  329. status = "disabled";
  330. };
  331. &tscadc0 {
  332. adc {
  333. ti,adc-channels = <0 1 2 3 4 5 6 7>;
  334. };
  335. };
  336. &tscadc1 {
  337. adc {
  338. ti,adc-channels = <0 1 2 3 4 5 6 7>;
  339. };
  340. };
  341. &serdes0 {
  342. status = "disabled";
  343. };
  344. &serdes1 {
  345. status = "disabled";
  346. };
  347. &pcie0_rc {
  348. status = "disabled";
  349. };
  350. &pcie0_ep {
  351. status = "disabled";
  352. };
  353. &pcie1_rc {
  354. status = "disabled";
  355. };
  356. &pcie1_ep {
  357. status = "disabled";
  358. };
  359. &m_can0 {
  360. status = "disabled";
  361. };
  362. &m_can1 {
  363. status = "disabled";
  364. };
  365. &mailbox0_cluster0 {
  366. interrupts = <436>;
  367. mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
  368. ti,mbox-tx = <1 0 0>;
  369. ti,mbox-rx = <0 0 0>;
  370. };
  371. };
  372. &mailbox0_cluster1 {
  373. interrupts = <432>;
  374. mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
  375. ti,mbox-tx = <1 0 0>;
  376. ti,mbox-rx = <0 0 0>;
  377. };
  378. };
  379. &mailbox0_cluster2 {
  380. status = "disabled";
  381. };
  382. &mailbox0_cluster3 {
  383. status = "disabled";
  384. };
  385. &mailbox0_cluster4 {
  386. status = "disabled";
  387. };
  388. &mailbox0_cluster5 {
  389. status = "disabled";
  390. };
  391. &mailbox0_cluster6 {
  392. status = "disabled";
  393. };
  394. &mailbox0_cluster7 {
  395. status = "disabled";
  396. };
  397. &mailbox0_cluster8 {
  398. status = "disabled";
  399. };
  400. &mailbox0_cluster9 {
  401. status = "disabled";
  402. };
  403. &mailbox0_cluster10 {
  404. status = "disabled";
  405. };
  406. &mailbox0_cluster11 {
  407. status = "disabled";
  408. };
  409. &mcu_r5fss0_core0 {
  410. memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
  411. <&mcu_r5fss0_core0_memory_region>;
  412. mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
  413. };
  414. &mcu_r5fss0_core1 {
  415. memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
  416. <&mcu_r5fss0_core1_memory_region>;
  417. mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
  418. };
  419. &ospi0 {
  420. pinctrl-names = "default";
  421. pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
  422. flash@0 {
  423. compatible = "jedec,spi-nor";
  424. reg = <0x0>;
  425. spi-tx-bus-width = <8>;
  426. spi-rx-bus-width = <8>;
  427. spi-max-frequency = <25000000>;
  428. cdns,tshsl-ns = <60>;
  429. cdns,tsd2d-ns = <60>;
  430. cdns,tchsh-ns = <60>;
  431. cdns,tslch-ns = <60>;
  432. cdns,read-delay = <0>;
  433. };
  434. };
  435. &mcu_cpsw {
  436. pinctrl-names = "default";
  437. pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
  438. };
  439. &davinci_mdio {
  440. phy0: ethernet-phy@0 {
  441. reg = <0>;
  442. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  443. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  444. };
  445. };
  446. &cpsw_port1 {
  447. phy-mode = "rgmii-rxid";
  448. phy-handle = <&phy0>;
  449. };
  450. &mcasp0 {
  451. status = "disabled";
  452. };
  453. &mcasp1 {
  454. status = "disabled";
  455. };
  456. &mcasp2 {
  457. status = "disabled";
  458. };
  459. &dss {
  460. status = "disabled";
  461. };
  462. &icssg0_mdio {
  463. status = "disabled";
  464. };
  465. &icssg1_mdio {
  466. status = "disabled";
  467. };
  468. &icssg2_mdio {
  469. status = "disabled";
  470. };