k3-am65-iot2050-common-pg2.dtsi 1.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) Siemens AG, 2021
  4. *
  5. * Authors:
  6. * Chao Zeng <[email protected]>
  7. * Jan Kiszka <[email protected]>
  8. *
  9. * Common bits of the IOT2050 Basic and Advanced variants, PG2
  10. */
  11. &main_pmx0 {
  12. cp2102n_reset_pin_default: cp2102n-reset-pin-default {
  13. pinctrl-single,pins = <
  14. /* (AF12) GPIO1_24, used as cp2102 reset */
  15. AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
  16. >;
  17. };
  18. };
  19. &main_gpio1 {
  20. pinctrl-names = "default";
  21. pinctrl-0 = <&cp2102n_reset_pin_default>;
  22. gpio-line-names =
  23. "", "", "", "", "", "", "", "", "", "",
  24. "", "", "", "", "", "", "", "", "", "",
  25. "", "", "", "", "CP2102N-RESET";
  26. };
  27. &dss {
  28. /* Workaround needed to get DP clock of 154Mhz */
  29. assigned-clocks = <&k3_clks 67 0>;
  30. };
  31. &serdes0 {
  32. assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
  33. assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
  34. };
  35. &dwc3_0 {
  36. assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
  37. <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
  38. phys = <&serdes0 PHY_TYPE_USB3 0>;
  39. phy-names = "usb3-phy";
  40. };
  41. &usb0 {
  42. maximum-speed = "super-speed";
  43. snps,dis-u1-entry-quirk;
  44. snps,dis-u2-entry-quirk;
  45. };