k3-am642.dtsi 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for AM642 SoC family in Dual core configuration
  4. *
  5. * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
  6. */
  7. /dts-v1/;
  8. #include "k3-am64.dtsi"
  9. / {
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. cpu-map {
  14. cluster0: cluster0 {
  15. core0 {
  16. cpu = <&cpu0>;
  17. };
  18. core1 {
  19. cpu = <&cpu1>;
  20. };
  21. };
  22. };
  23. cpu0: cpu@0 {
  24. compatible = "arm,cortex-a53";
  25. reg = <0x000>;
  26. device_type = "cpu";
  27. enable-method = "psci";
  28. i-cache-size = <0x8000>;
  29. i-cache-line-size = <64>;
  30. i-cache-sets = <256>;
  31. d-cache-size = <0x8000>;
  32. d-cache-line-size = <64>;
  33. d-cache-sets = <128>;
  34. next-level-cache = <&L2_0>;
  35. };
  36. cpu1: cpu@1 {
  37. compatible = "arm,cortex-a53";
  38. reg = <0x001>;
  39. device_type = "cpu";
  40. enable-method = "psci";
  41. i-cache-size = <0x8000>;
  42. i-cache-line-size = <64>;
  43. i-cache-sets = <256>;
  44. d-cache-size = <0x8000>;
  45. d-cache-line-size = <64>;
  46. d-cache-sets = <128>;
  47. next-level-cache = <&L2_0>;
  48. };
  49. };
  50. L2_0: l2-cache0 {
  51. compatible = "cache";
  52. cache-level = <2>;
  53. cache-size = <0x40000>;
  54. cache-line-size = <64>;
  55. cache-sets = <256>;
  56. };
  57. };