k3-am64.dtsi 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for AM642 SoC Family
  4. *
  5. * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
  6. */
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/interrupt-controller/irq.h>
  9. #include <dt-bindings/interrupt-controller/arm-gic.h>
  10. #include <dt-bindings/pinctrl/k3.h>
  11. #include <dt-bindings/soc/ti,sci_pm_domain.h>
  12. / {
  13. model = "Texas Instruments K3 AM642 SoC";
  14. compatible = "ti,am642";
  15. interrupt-parent = <&gic500>;
  16. #address-cells = <2>;
  17. #size-cells = <2>;
  18. aliases {
  19. serial0 = &mcu_uart0;
  20. serial1 = &mcu_uart1;
  21. serial2 = &main_uart0;
  22. serial3 = &main_uart1;
  23. serial4 = &main_uart2;
  24. serial5 = &main_uart3;
  25. serial6 = &main_uart4;
  26. serial7 = &main_uart5;
  27. serial8 = &main_uart6;
  28. ethernet0 = &cpsw_port1;
  29. ethernet1 = &cpsw_port2;
  30. mmc0 = &sdhci0;
  31. mmc1 = &sdhci1;
  32. };
  33. chosen { };
  34. firmware {
  35. optee {
  36. compatible = "linaro,optee-tz";
  37. method = "smc";
  38. };
  39. psci: psci {
  40. compatible = "arm,psci-1.0";
  41. method = "smc";
  42. };
  43. };
  44. a53_timer0: timer-cl0-cpu0 {
  45. compatible = "arm,armv8-timer";
  46. interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
  47. <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
  48. <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
  49. <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
  50. };
  51. pmu: pmu {
  52. compatible = "arm,cortex-a53-pmu";
  53. interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  54. };
  55. cbass_main: bus@f4000 {
  56. compatible = "simple-bus";
  57. #address-cells = <2>;
  58. #size-cells = <2>;
  59. ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
  60. <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
  61. <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
  62. <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
  63. <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
  64. <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
  65. <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
  66. <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
  67. <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
  68. <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
  69. <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
  70. <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
  71. <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
  72. <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
  73. <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
  74. <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
  75. <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
  76. <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
  77. <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
  78. <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
  79. <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
  80. <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
  81. <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
  82. <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
  83. <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
  84. <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
  85. <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
  86. <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
  87. <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
  88. /* MCU Domain Range */
  89. <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
  90. cbass_mcu: bus@4000000 {
  91. compatible = "simple-bus";
  92. #address-cells = <2>;
  93. #size-cells = <2>;
  94. ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
  95. };
  96. };
  97. };
  98. /* Now include the peripherals for each bus segments */
  99. #include "k3-am64-main.dtsi"
  100. #include "k3-am64-mcu.dtsi"