k3-am64-mcu.dtsi 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for AM64 SoC Family MCU Domain peripherals
  4. *
  5. * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
  6. */
  7. &cbass_mcu {
  8. mcu_uart0: serial@4a00000 {
  9. compatible = "ti,am64-uart", "ti,am654-uart";
  10. reg = <0x00 0x04a00000 0x00 0x100>;
  11. interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
  12. current-speed = <115200>;
  13. power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  14. clocks = <&k3_clks 149 0>;
  15. clock-names = "fclk";
  16. };
  17. mcu_uart1: serial@4a10000 {
  18. compatible = "ti,am64-uart", "ti,am654-uart";
  19. reg = <0x00 0x04a10000 0x00 0x100>;
  20. interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
  21. current-speed = <115200>;
  22. power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
  23. clocks = <&k3_clks 160 0>;
  24. clock-names = "fclk";
  25. };
  26. mcu_i2c0: i2c@4900000 {
  27. compatible = "ti,am64-i2c", "ti,omap4-i2c";
  28. reg = <0x00 0x04900000 0x00 0x100>;
  29. interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
  33. clocks = <&k3_clks 106 2>;
  34. clock-names = "fck";
  35. };
  36. mcu_i2c1: i2c@4910000 {
  37. compatible = "ti,am64-i2c", "ti,omap4-i2c";
  38. reg = <0x00 0x04910000 0x00 0x100>;
  39. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  40. #address-cells = <1>;
  41. #size-cells = <0>;
  42. power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
  43. clocks = <&k3_clks 107 2>;
  44. clock-names = "fck";
  45. };
  46. mcu_spi0: spi@4b00000 {
  47. compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
  48. reg = <0x00 0x04b00000 0x00 0x400>;
  49. interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
  50. #address-cells = <1>;
  51. #size-cells = <0>;
  52. power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
  53. clocks = <&k3_clks 147 0>;
  54. };
  55. mcu_spi1: spi@4b10000 {
  56. compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  57. reg = <0x00 0x04b10000 0x00 0x400>;
  58. interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
  59. #address-cells = <1>;
  60. #size-cells = <0>;
  61. power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
  62. clocks = <&k3_clks 148 0>;
  63. };
  64. mcu_gpio_intr: interrupt-controller@4210000 {
  65. compatible = "ti,sci-intr";
  66. reg = <0x00 0x04210000 0x00 0x200>;
  67. ti,intr-trigger-type = <1>;
  68. interrupt-controller;
  69. interrupt-parent = <&gic500>;
  70. #interrupt-cells = <1>;
  71. ti,sci = <&dmsc>;
  72. ti,sci-dev-id = <5>;
  73. ti,interrupt-ranges = <0 104 4>;
  74. };
  75. mcu_gpio0: gpio@4201000 {
  76. compatible = "ti,am64-gpio", "ti,keystone-gpio";
  77. reg = <0x0 0x4201000 0x0 0x100>;
  78. gpio-controller;
  79. #gpio-cells = <2>;
  80. interrupt-parent = <&mcu_gpio_intr>;
  81. interrupts = <30>, <31>;
  82. interrupt-controller;
  83. #interrupt-cells = <2>;
  84. ti,ngpio = <23>;
  85. ti,davinci-gpio-unbanked = <0>;
  86. power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
  87. clocks = <&k3_clks 79 0>;
  88. clock-names = "gpio";
  89. };
  90. mcu_pmx0: pinctrl@4084000 {
  91. compatible = "pinctrl-single";
  92. reg = <0x00 0x4084000 0x00 0x84>;
  93. #pinctrl-cells = <1>;
  94. pinctrl-single,register-width = <32>;
  95. pinctrl-single,function-mask = <0xffffffff>;
  96. };
  97. };