k3-am625-sk.dts 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * AM625 SK: https://www.ti.com/lit/zip/sprr448
  4. *
  5. * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
  6. */
  7. /dts-v1/;
  8. #include <dt-bindings/leds/common.h>
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/net/ti-dp83867.h>
  11. #include "k3-am625.dtsi"
  12. / {
  13. compatible = "ti,am625-sk", "ti,am625";
  14. model = "Texas Instruments AM625 SK";
  15. aliases {
  16. serial2 = &main_uart0;
  17. mmc0 = &sdhci0;
  18. mmc1 = &sdhci1;
  19. mmc2 = &sdhci2;
  20. spi0 = &ospi0;
  21. ethernet0 = &cpsw_port1;
  22. ethernet1 = &cpsw_port2;
  23. };
  24. chosen {
  25. stdout-path = "serial2:115200n8";
  26. bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
  27. };
  28. memory@80000000 {
  29. device_type = "memory";
  30. /* 2G RAM */
  31. reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
  32. };
  33. reserved-memory {
  34. #address-cells = <2>;
  35. #size-cells = <2>;
  36. ranges;
  37. ramoops@9ca00000 {
  38. compatible = "ramoops";
  39. reg = <0x00 0x9ca00000 0x00 0x00100000>;
  40. record-size = <0x8000>;
  41. console-size = <0x8000>;
  42. ftrace-size = <0x00>;
  43. pmsg-size = <0x8000>;
  44. };
  45. secure_tfa_ddr: tfa@9e780000 {
  46. reg = <0x00 0x9e780000 0x00 0x80000>;
  47. alignment = <0x1000>;
  48. no-map;
  49. };
  50. secure_ddr: optee@9e800000 {
  51. reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
  52. alignment = <0x1000>;
  53. no-map;
  54. };
  55. wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
  56. compatible = "shared-dma-pool";
  57. reg = <0x00 0x9db00000 0x00 0xc00000>;
  58. no-map;
  59. };
  60. };
  61. vmain_pd: regulator-0 {
  62. /* TPS65988 PD CONTROLLER OUTPUT */
  63. compatible = "regulator-fixed";
  64. regulator-name = "vmain_pd";
  65. regulator-min-microvolt = <5000000>;
  66. regulator-max-microvolt = <5000000>;
  67. regulator-always-on;
  68. regulator-boot-on;
  69. };
  70. vcc_5v0: regulator-1 {
  71. /* Output of LM34936 */
  72. compatible = "regulator-fixed";
  73. regulator-name = "vcc_5v0";
  74. regulator-min-microvolt = <5000000>;
  75. regulator-max-microvolt = <5000000>;
  76. vin-supply = <&vmain_pd>;
  77. regulator-always-on;
  78. regulator-boot-on;
  79. };
  80. vcc_3v3_sys: regulator-2 {
  81. /* output of LM61460-Q1 */
  82. compatible = "regulator-fixed";
  83. regulator-name = "vcc_3v3_sys";
  84. regulator-min-microvolt = <3300000>;
  85. regulator-max-microvolt = <3300000>;
  86. vin-supply = <&vmain_pd>;
  87. regulator-always-on;
  88. regulator-boot-on;
  89. };
  90. vdd_mmc1: regulator-3 {
  91. /* TPS22918DBVR */
  92. compatible = "regulator-fixed";
  93. regulator-name = "vdd_mmc1";
  94. regulator-min-microvolt = <3300000>;
  95. regulator-max-microvolt = <3300000>;
  96. regulator-boot-on;
  97. enable-active-high;
  98. vin-supply = <&vcc_3v3_sys>;
  99. gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
  100. };
  101. vdd_sd_dv: regulator-4 {
  102. /* Output of TLV71033 */
  103. compatible = "regulator-gpio";
  104. regulator-name = "tlv71033";
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&vdd_sd_dv_pins_default>;
  107. regulator-min-microvolt = <1800000>;
  108. regulator-max-microvolt = <3300000>;
  109. regulator-boot-on;
  110. vin-supply = <&vcc_5v0>;
  111. gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
  112. states = <1800000 0x0>,
  113. <3300000 0x1>;
  114. };
  115. leds {
  116. compatible = "gpio-leds";
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&usr_led_pins_default>;
  119. led-0 {
  120. label = "am62-sk:green:heartbeat";
  121. gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
  122. linux,default-trigger = "heartbeat";
  123. function = LED_FUNCTION_HEARTBEAT;
  124. default-state = "off";
  125. };
  126. };
  127. };
  128. &main_pmx0 {
  129. main_uart0_pins_default: main-uart0-pins-default {
  130. pinctrl-single,pins = <
  131. AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
  132. AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
  133. >;
  134. };
  135. main_i2c0_pins_default: main-i2c0-pins-default {
  136. pinctrl-single,pins = <
  137. AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
  138. AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
  139. >;
  140. };
  141. main_i2c1_pins_default: main-i2c1-pins-default {
  142. pinctrl-single,pins = <
  143. AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
  144. AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
  145. >;
  146. };
  147. main_i2c2_pins_default: main-i2c2-pins-default {
  148. pinctrl-single,pins = <
  149. AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
  150. AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
  151. >;
  152. };
  153. main_mmc0_pins_default: main-mmc0-pins-default {
  154. pinctrl-single,pins = <
  155. AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
  156. AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
  157. AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
  158. AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
  159. AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
  160. AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
  161. AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
  162. AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
  163. AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
  164. AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
  165. >;
  166. };
  167. main_mmc1_pins_default: main-mmc1-pins-default {
  168. pinctrl-single,pins = <
  169. AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
  170. AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
  171. AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
  172. AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
  173. AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
  174. AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
  175. AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
  176. >;
  177. };
  178. usr_led_pins_default: usr-led-pins-default {
  179. pinctrl-single,pins = <
  180. AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
  181. >;
  182. };
  183. main_mdio1_pins_default: main-mdio1-pins-default {
  184. pinctrl-single,pins = <
  185. AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
  186. AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
  187. >;
  188. };
  189. main_rgmii1_pins_default: main-rgmii1-pins-default {
  190. pinctrl-single,pins = <
  191. AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
  192. AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
  193. AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
  194. AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
  195. AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
  196. AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
  197. AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
  198. AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
  199. AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
  200. AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
  201. AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
  202. AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
  203. >;
  204. };
  205. main_rgmii2_pins_default: main-rgmii2-pins-default {
  206. pinctrl-single,pins = <
  207. AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
  208. AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
  209. AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
  210. AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
  211. AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
  212. AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
  213. AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
  214. AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
  215. AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
  216. AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
  217. AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
  218. AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
  219. >;
  220. };
  221. ospi0_pins_default: ospi0-pins-default {
  222. pinctrl-single,pins = <
  223. AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
  224. AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
  225. AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
  226. AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
  227. AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
  228. AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
  229. AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
  230. AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
  231. AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
  232. AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
  233. AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
  234. >;
  235. };
  236. vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
  237. pinctrl-single,pins = <
  238. AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
  239. >;
  240. };
  241. main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
  242. pinctrl-single,pins = <
  243. AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
  244. >;
  245. };
  246. };
  247. &wkup_uart0 {
  248. /* WKUP UART0 is used by DM firmware */
  249. status = "reserved";
  250. };
  251. &mcu_uart0 {
  252. status = "disabled";
  253. };
  254. &main_uart0 {
  255. pinctrl-names = "default";
  256. pinctrl-0 = <&main_uart0_pins_default>;
  257. };
  258. &main_uart1 {
  259. /* Main UART1 is used by TIFS firmware */
  260. status = "reserved";
  261. };
  262. &main_uart2 {
  263. status = "disabled";
  264. };
  265. &main_uart3 {
  266. status = "disabled";
  267. };
  268. &main_uart4 {
  269. status = "disabled";
  270. };
  271. &main_uart5 {
  272. status = "disabled";
  273. };
  274. &main_uart6 {
  275. status = "disabled";
  276. };
  277. &mcu_i2c0 {
  278. status = "disabled";
  279. };
  280. &wkup_i2c0 {
  281. status = "disabled";
  282. };
  283. &main_i2c0 {
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&main_i2c0_pins_default>;
  286. clock-frequency = <400000>;
  287. };
  288. &main_i2c1 {
  289. pinctrl-names = "default";
  290. pinctrl-0 = <&main_i2c1_pins_default>;
  291. clock-frequency = <400000>;
  292. exp1: gpio@22 {
  293. compatible = "ti,tca6424";
  294. reg = <0x22>;
  295. gpio-controller;
  296. #gpio-cells = <2>;
  297. gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
  298. "PRU_DETECT", "MMC1_SD_EN",
  299. "VPP_LDO_EN", "EXP_PS_3V3_En",
  300. "EXP_PS_5V0_En", "EXP_HAT_DETECT",
  301. "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
  302. "UART1_FET_BUF_EN", "WL_LT_EN",
  303. "GPIO_HDMI_RSTn", "CSI_GPIO1",
  304. "CSI_GPIO2", "PRU_3V3_EN",
  305. "HDMI_INTn", "TEST_GPIO2",
  306. "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
  307. "MCASP1_FET_SEL", "UART1_FET_SEL",
  308. "TSINT#", "IO_EXP_TEST_LED";
  309. interrupt-parent = <&main_gpio1>;
  310. interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
  311. interrupt-controller;
  312. #interrupt-cells = <2>;
  313. pinctrl-names = "default";
  314. pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
  315. };
  316. };
  317. &main_i2c2 {
  318. status = "disabled";
  319. };
  320. &main_i2c3 {
  321. status = "disabled";
  322. };
  323. &sdhci0 {
  324. pinctrl-names = "default";
  325. pinctrl-0 = <&main_mmc0_pins_default>;
  326. ti,driver-strength-ohm = <50>;
  327. disable-wp;
  328. };
  329. &sdhci1 {
  330. /* SD/MMC */
  331. vmmc-supply = <&vdd_mmc1>;
  332. vqmmc-supply = <&vdd_sd_dv>;
  333. pinctrl-names = "default";
  334. pinctrl-0 = <&main_mmc1_pins_default>;
  335. ti,driver-strength-ohm = <50>;
  336. disable-wp;
  337. };
  338. &cpsw3g {
  339. pinctrl-names = "default";
  340. pinctrl-0 = <&main_mdio1_pins_default
  341. &main_rgmii1_pins_default
  342. &main_rgmii2_pins_default>;
  343. };
  344. &cpsw_port1 {
  345. phy-mode = "rgmii-rxid";
  346. phy-handle = <&cpsw3g_phy0>;
  347. };
  348. &cpsw_port2 {
  349. phy-mode = "rgmii-rxid";
  350. phy-handle = <&cpsw3g_phy1>;
  351. };
  352. &cpsw3g_mdio {
  353. cpsw3g_phy0: ethernet-phy@0 {
  354. reg = <0>;
  355. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  356. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  357. ti,min-output-impedance;
  358. };
  359. cpsw3g_phy1: ethernet-phy@1 {
  360. reg = <1>;
  361. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  362. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  363. ti,min-output-impedance;
  364. };
  365. };
  366. &mailbox0_cluster0 {
  367. mbox_m4_0: mbox-m4-0 {
  368. ti,mbox-rx = <0 0 0>;
  369. ti,mbox-tx = <1 0 0>;
  370. };
  371. };
  372. &ospi0 {
  373. pinctrl-names = "default";
  374. pinctrl-0 = <&ospi0_pins_default>;
  375. flash@0{
  376. compatible = "jedec,spi-nor";
  377. reg = <0x0>;
  378. spi-tx-bus-width = <8>;
  379. spi-rx-bus-width = <8>;
  380. spi-max-frequency = <25000000>;
  381. cdns,tshsl-ns = <60>;
  382. cdns,tsd2d-ns = <60>;
  383. cdns,tchsh-ns = <60>;
  384. cdns,tslch-ns = <60>;
  385. cdns,read-delay = <4>;
  386. partitions {
  387. compatible = "fixed-partitions";
  388. #address-cells = <1>;
  389. #size-cells = <1>;
  390. partition@0 {
  391. label = "ospi.tiboot3";
  392. reg = <0x0 0x80000>;
  393. };
  394. partition@80000 {
  395. label = "ospi.tispl";
  396. reg = <0x80000 0x200000>;
  397. };
  398. partition@280000 {
  399. label = "ospi.u-boot";
  400. reg = <0x280000 0x400000>;
  401. };
  402. partition@680000 {
  403. label = "ospi.env";
  404. reg = <0x680000 0x40000>;
  405. };
  406. partition@6c0000 {
  407. label = "ospi.env.backup";
  408. reg = <0x6c0000 0x40000>;
  409. };
  410. partition@800000 {
  411. label = "ospi.rootfs";
  412. reg = <0x800000 0x37c0000>;
  413. };
  414. partition@3fc0000 {
  415. label = "ospi.phypattern";
  416. reg = <0x3fc0000 0x40000>;
  417. };
  418. };
  419. };
  420. };
  421. &ecap0 {
  422. status = "disabled";
  423. };
  424. &ecap1 {
  425. status = "disabled";
  426. };
  427. &ecap2 {
  428. status = "disabled";
  429. };
  430. &main_mcan0 {
  431. status = "disabled";
  432. };
  433. &epwm0 {
  434. status = "disabled";
  435. };
  436. &epwm1 {
  437. status = "disabled";
  438. };
  439. &epwm2 {
  440. status = "disabled";
  441. };