uniphier-pxs3-ref.dts 2.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162
  1. // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2. //
  3. // Device Tree Source for UniPhier PXs3 Reference Board
  4. //
  5. // Copyright (C) 2017 Socionext Inc.
  6. // Author: Masahiro Yamada <[email protected]>
  7. /dts-v1/;
  8. #include "uniphier-pxs3.dtsi"
  9. #include "uniphier-support-card.dtsi"
  10. / {
  11. model = "UniPhier PXs3 Reference Board";
  12. compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
  13. chosen {
  14. stdout-path = "serial0:115200n8";
  15. };
  16. aliases {
  17. serial0 = &serial0;
  18. serial1 = &serialsc;
  19. serial2 = &serial2;
  20. serial3 = &serial3;
  21. i2c0 = &i2c0;
  22. i2c1 = &i2c1;
  23. i2c2 = &i2c2;
  24. i2c3 = &i2c3;
  25. i2c6 = &i2c6;
  26. spi0 = &spi0;
  27. spi1 = &spi1;
  28. ethernet0 = &eth0;
  29. ethernet1 = &eth1;
  30. };
  31. memory@80000000 {
  32. device_type = "memory";
  33. reg = <0 0x80000000 0 0xa0000000>;
  34. };
  35. };
  36. &ethsc {
  37. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  38. };
  39. &serialsc {
  40. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  41. };
  42. &spi0 {
  43. status = "okay";
  44. };
  45. &spi1 {
  46. status = "okay";
  47. };
  48. &serial0 {
  49. status = "okay";
  50. };
  51. &serial2 {
  52. status = "okay";
  53. };
  54. &serial3 {
  55. status = "okay";
  56. };
  57. &gpio {
  58. xirq4-hog {
  59. gpio-hog;
  60. gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
  61. input;
  62. };
  63. };
  64. &i2c0 {
  65. status = "okay";
  66. };
  67. &i2c1 {
  68. status = "okay";
  69. };
  70. &i2c2 {
  71. status = "okay";
  72. };
  73. &i2c3 {
  74. status = "okay";
  75. };
  76. &sd {
  77. status = "okay";
  78. };
  79. &eth0 {
  80. status = "okay";
  81. phy-handle = <&ethphy0>;
  82. };
  83. &mdio0 {
  84. ethphy0: ethernet-phy@0 {
  85. reg = <0>;
  86. };
  87. };
  88. &eth1 {
  89. status = "okay";
  90. phy-handle = <&ethphy1>;
  91. };
  92. &mdio1 {
  93. ethphy1: ethernet-phy@0 {
  94. reg = <0>;
  95. };
  96. };
  97. &usb0 {
  98. status = "okay";
  99. };
  100. &usb1 {
  101. status = "okay";
  102. };
  103. &pcie {
  104. status = "okay";
  105. };
  106. &nand {
  107. status = "okay";
  108. nand@0 {
  109. reg = <0>;
  110. };
  111. };
  112. &ahci0 {
  113. status = "okay";
  114. };
  115. &ahci1 {
  116. status = "okay";
  117. };
  118. &pinctrl_ether_rgmii {
  119. tx {
  120. pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
  121. "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL";
  122. drive-strength = <9>;
  123. };
  124. };
  125. &pinctrl_ether1_rgmii {
  126. tx {
  127. pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1",
  128. "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL";
  129. drive-strength = <9>;
  130. };
  131. };