uniphier-ld20-ref.dts 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2. //
  3. // Device Tree Source for UniPhier LD20 Reference Board
  4. //
  5. // Copyright (C) 2015-2016 Socionext Inc.
  6. // Author: Masahiro Yamada <[email protected]>
  7. /dts-v1/;
  8. #include "uniphier-ld20.dtsi"
  9. #include "uniphier-ref-daughter.dtsi"
  10. #include "uniphier-support-card.dtsi"
  11. / {
  12. model = "UniPhier LD20 Reference Board";
  13. compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
  14. chosen {
  15. stdout-path = "serial0:115200n8";
  16. };
  17. aliases {
  18. serial0 = &serial0;
  19. serial1 = &serialsc;
  20. serial2 = &serial2;
  21. serial3 = &serial3;
  22. i2c0 = &i2c0;
  23. i2c1 = &i2c1;
  24. i2c2 = &i2c2;
  25. i2c3 = &i2c3;
  26. i2c4 = &i2c4;
  27. i2c5 = &i2c5;
  28. ethernet0 = &eth;
  29. };
  30. memory@80000000 {
  31. device_type = "memory";
  32. reg = <0 0x80000000 0 0xc0000000>;
  33. };
  34. };
  35. &ethsc {
  36. interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  37. };
  38. &serialsc {
  39. interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  40. };
  41. &serial0 {
  42. status = "okay";
  43. };
  44. &gpio {
  45. xirq0-hog {
  46. gpio-hog;
  47. gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
  48. input;
  49. };
  50. };
  51. &i2c0 {
  52. status = "okay";
  53. };
  54. &eth {
  55. status = "okay";
  56. phy-handle = <&ethphy>;
  57. };
  58. &mdio {
  59. ethphy: ethernet-phy@0 {
  60. reg = <0>;
  61. };
  62. };
  63. &pinctrl_ether_rgmii {
  64. tx {
  65. pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
  66. "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
  67. drive-strength = <9>;
  68. };
  69. };
  70. &usb {
  71. status = "okay";
  72. };