rk3568-bpi-r2-pro.dts 17 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Author: Frank Wunderlich <[email protected]>
  4. *
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/leds/common.h>
  9. #include <dt-bindings/pinctrl/rockchip.h>
  10. #include <dt-bindings/soc/rockchip,vop2.h>
  11. #include "rk3568.dtsi"
  12. / {
  13. model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
  14. compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
  15. aliases {
  16. ethernet0 = &gmac0;
  17. ethernet1 = &gmac1;
  18. mmc0 = &sdmmc0;
  19. mmc1 = &sdhci;
  20. };
  21. chosen: chosen {
  22. stdout-path = "serial2:1500000n8";
  23. };
  24. leds {
  25. compatible = "gpio-leds";
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&blue_led_pin &green_led_pin>;
  28. blue_led: led-0 {
  29. color = <LED_COLOR_ID_BLUE>;
  30. default-state = "off";
  31. function = LED_FUNCTION_STATUS;
  32. gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
  33. };
  34. green_led: led-1 {
  35. color = <LED_COLOR_ID_GREEN>;
  36. default-state = "on";
  37. function = LED_FUNCTION_POWER;
  38. gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
  39. };
  40. };
  41. dc_12v: dc-12v-regulator {
  42. compatible = "regulator-fixed";
  43. regulator-name = "dc_12v";
  44. regulator-always-on;
  45. regulator-boot-on;
  46. regulator-min-microvolt = <12000000>;
  47. regulator-max-microvolt = <12000000>;
  48. };
  49. hdmi-con {
  50. compatible = "hdmi-connector";
  51. type = "a";
  52. port {
  53. hdmi_con_in: endpoint {
  54. remote-endpoint = <&hdmi_out_con>;
  55. };
  56. };
  57. };
  58. vcc3v3_sys: vcc3v3-sys-regulator {
  59. compatible = "regulator-fixed";
  60. regulator-name = "vcc3v3_sys";
  61. regulator-always-on;
  62. regulator-boot-on;
  63. regulator-min-microvolt = <3300000>;
  64. regulator-max-microvolt = <3300000>;
  65. vin-supply = <&dc_12v>;
  66. };
  67. vcc5v0_sys: vcc5v0-sys-regulator {
  68. compatible = "regulator-fixed";
  69. regulator-name = "vcc5v0_sys";
  70. regulator-always-on;
  71. regulator-boot-on;
  72. regulator-min-microvolt = <5000000>;
  73. regulator-max-microvolt = <5000000>;
  74. vin-supply = <&dc_12v>;
  75. };
  76. pcie30_avdd0v9: pcie30-avdd0v9-regulator {
  77. compatible = "regulator-fixed";
  78. regulator-name = "pcie30_avdd0v9";
  79. regulator-always-on;
  80. regulator-boot-on;
  81. regulator-min-microvolt = <900000>;
  82. regulator-max-microvolt = <900000>;
  83. vin-supply = <&vcc3v3_sys>;
  84. };
  85. pcie30_avdd1v8: pcie30-avdd1v8-regulator {
  86. compatible = "regulator-fixed";
  87. regulator-name = "pcie30_avdd1v8";
  88. regulator-always-on;
  89. regulator-boot-on;
  90. regulator-min-microvolt = <1800000>;
  91. regulator-max-microvolt = <1800000>;
  92. vin-supply = <&vcc3v3_sys>;
  93. };
  94. /* pi6c pcie clock generator feeds both ports */
  95. vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
  96. compatible = "regulator-fixed";
  97. regulator-name = "vcc3v3_pcie";
  98. regulator-min-microvolt = <3300000>;
  99. regulator-max-microvolt = <3300000>;
  100. enable-active-high;
  101. gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
  102. startup-delay-us = <200000>;
  103. vin-supply = <&vcc5v0_sys>;
  104. };
  105. /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
  106. vcc3v3_minipcie: vcc3v3-minipcie-regulator {
  107. compatible = "regulator-fixed";
  108. regulator-name = "vcc3v3_minipcie";
  109. regulator-min-microvolt = <3300000>;
  110. regulator-max-microvolt = <3300000>;
  111. enable-active-high;
  112. gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
  113. pinctrl-names = "default";
  114. pinctrl-0 = <&minipcie_enable_h>;
  115. startup-delay-us = <50000>;
  116. vin-supply = <&vcc3v3_pi6c_05>;
  117. };
  118. /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
  119. vcc3v3_ngff: vcc3v3-ngff-regulator {
  120. compatible = "regulator-fixed";
  121. regulator-name = "vcc3v3_ngff";
  122. regulator-min-microvolt = <3300000>;
  123. regulator-max-microvolt = <3300000>;
  124. enable-active-high;
  125. gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
  126. pinctrl-names = "default";
  127. pinctrl-0 = <&ngffpcie_enable_h>;
  128. startup-delay-us = <50000>;
  129. vin-supply = <&vcc3v3_pi6c_05>;
  130. };
  131. vcc5v0_usb: vcc5v0-usb-regulator {
  132. compatible = "regulator-fixed";
  133. regulator-name = "vcc5v0_usb";
  134. regulator-always-on;
  135. regulator-boot-on;
  136. regulator-min-microvolt = <5000000>;
  137. regulator-max-microvolt = <5000000>;
  138. vin-supply = <&dc_12v>;
  139. };
  140. vcc5v0_usb_host: vcc5v0-usb-host-regulator {
  141. compatible = "regulator-fixed";
  142. enable-active-high;
  143. gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
  144. pinctrl-names = "default";
  145. pinctrl-0 = <&vcc5v0_usb_host_en>;
  146. regulator-name = "vcc5v0_usb_host";
  147. regulator-min-microvolt = <5000000>;
  148. regulator-max-microvolt = <5000000>;
  149. vin-supply = <&vcc5v0_usb>;
  150. };
  151. vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
  152. compatible = "regulator-fixed";
  153. enable-active-high;
  154. gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&vcc5v0_usb_otg_en>;
  157. regulator-name = "vcc5v0_usb_otg";
  158. regulator-min-microvolt = <5000000>;
  159. regulator-max-microvolt = <5000000>;
  160. vin-supply = <&vcc5v0_usb>;
  161. };
  162. };
  163. &combphy0 {
  164. /* used for USB3 */
  165. status = "okay";
  166. };
  167. &combphy1 {
  168. /* used for USB3 */
  169. status = "okay";
  170. };
  171. &combphy2 {
  172. /* used for SATA */
  173. status = "okay";
  174. };
  175. &gmac0 {
  176. assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
  177. assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
  178. clock_in_out = "input";
  179. phy-mode = "rgmii";
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&gmac0_miim
  182. &gmac0_tx_bus2
  183. &gmac0_rx_bus2
  184. &gmac0_rgmii_clk
  185. &gmac0_rgmii_bus>;
  186. snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
  187. snps,reset-active-low;
  188. /* Reset time is 20ms, 100ms for rtl8211f */
  189. snps,reset-delays-us = <0 20000 100000>;
  190. tx_delay = <0x4f>;
  191. rx_delay = <0x0f>;
  192. status = "okay";
  193. fixed-link {
  194. speed = <1000>;
  195. full-duplex;
  196. pause;
  197. };
  198. };
  199. &gmac1 {
  200. assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
  201. assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
  202. clock_in_out = "output";
  203. phy-handle = <&rgmii_phy1>;
  204. phy-mode = "rgmii";
  205. pinctrl-names = "default";
  206. pinctrl-0 = <&gmac1m1_miim
  207. &gmac1m1_tx_bus2
  208. &gmac1m1_rx_bus2
  209. &gmac1m1_rgmii_clk
  210. &gmac1m1_rgmii_bus>;
  211. snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
  212. snps,reset-active-low;
  213. /* Reset time is 20ms, 100ms for rtl8211f */
  214. snps,reset-delays-us = <0 20000 100000>;
  215. tx_delay = <0x3c>;
  216. rx_delay = <0x2f>;
  217. status = "okay";
  218. };
  219. &gpu {
  220. mali-supply = <&vdd_gpu>;
  221. status = "okay";
  222. };
  223. &hdmi {
  224. avdd-0v9-supply = <&vdda0v9_image>;
  225. avdd-1v8-supply = <&vcca1v8_image>;
  226. status = "okay";
  227. };
  228. &hdmi_in {
  229. hdmi_in_vp0: endpoint {
  230. remote-endpoint = <&vp0_out_hdmi>;
  231. };
  232. };
  233. &hdmi_out {
  234. hdmi_out_con: endpoint {
  235. remote-endpoint = <&hdmi_con_in>;
  236. };
  237. };
  238. &hdmi_sound {
  239. status = "okay";
  240. };
  241. &i2c0 {
  242. status = "okay";
  243. rk809: pmic@20 {
  244. compatible = "rockchip,rk809";
  245. reg = <0x20>;
  246. interrupt-parent = <&gpio0>;
  247. interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
  248. #clock-cells = <1>;
  249. pinctrl-names = "default";
  250. pinctrl-0 = <&pmic_int>;
  251. rockchip,system-power-controller;
  252. vcc1-supply = <&vcc3v3_sys>;
  253. vcc2-supply = <&vcc3v3_sys>;
  254. vcc3-supply = <&vcc3v3_sys>;
  255. vcc4-supply = <&vcc3v3_sys>;
  256. vcc5-supply = <&vcc3v3_sys>;
  257. vcc6-supply = <&vcc3v3_sys>;
  258. vcc7-supply = <&vcc3v3_sys>;
  259. vcc8-supply = <&vcc3v3_sys>;
  260. vcc9-supply = <&vcc3v3_sys>;
  261. wakeup-source;
  262. regulators {
  263. vdd_logic: DCDC_REG1 {
  264. regulator-name = "vdd_logic";
  265. regulator-always-on;
  266. regulator-boot-on;
  267. regulator-init-microvolt = <900000>;
  268. regulator-initial-mode = <0x2>;
  269. regulator-min-microvolt = <500000>;
  270. regulator-max-microvolt = <1350000>;
  271. regulator-ramp-delay = <6001>;
  272. regulator-state-mem {
  273. regulator-off-in-suspend;
  274. };
  275. };
  276. vdd_gpu: DCDC_REG2 {
  277. regulator-name = "vdd_gpu";
  278. regulator-always-on;
  279. regulator-init-microvolt = <900000>;
  280. regulator-initial-mode = <0x2>;
  281. regulator-min-microvolt = <500000>;
  282. regulator-max-microvolt = <1350000>;
  283. regulator-ramp-delay = <6001>;
  284. regulator-state-mem {
  285. regulator-off-in-suspend;
  286. };
  287. };
  288. vcc_ddr: DCDC_REG3 {
  289. regulator-name = "vcc_ddr";
  290. regulator-always-on;
  291. regulator-boot-on;
  292. regulator-initial-mode = <0x2>;
  293. regulator-state-mem {
  294. regulator-on-in-suspend;
  295. };
  296. };
  297. vdd_npu: DCDC_REG4 {
  298. regulator-name = "vdd_npu";
  299. regulator-init-microvolt = <900000>;
  300. regulator-initial-mode = <0x2>;
  301. regulator-min-microvolt = <500000>;
  302. regulator-max-microvolt = <1350000>;
  303. regulator-ramp-delay = <6001>;
  304. regulator-state-mem {
  305. regulator-off-in-suspend;
  306. };
  307. };
  308. vcc_1v8: DCDC_REG5 {
  309. regulator-name = "vcc_1v8";
  310. regulator-always-on;
  311. regulator-boot-on;
  312. regulator-min-microvolt = <1800000>;
  313. regulator-max-microvolt = <1800000>;
  314. regulator-state-mem {
  315. regulator-off-in-suspend;
  316. };
  317. };
  318. vdda0v9_image: LDO_REG1 {
  319. regulator-name = "vdda0v9_image";
  320. regulator-always-on;
  321. regulator-min-microvolt = <900000>;
  322. regulator-max-microvolt = <900000>;
  323. regulator-state-mem {
  324. regulator-off-in-suspend;
  325. };
  326. };
  327. vdda_0v9: LDO_REG2 {
  328. regulator-name = "vdda_0v9";
  329. regulator-always-on;
  330. regulator-boot-on;
  331. regulator-min-microvolt = <900000>;
  332. regulator-max-microvolt = <900000>;
  333. regulator-state-mem {
  334. regulator-off-in-suspend;
  335. };
  336. };
  337. vdda0v9_pmu: LDO_REG3 {
  338. regulator-name = "vdda0v9_pmu";
  339. regulator-always-on;
  340. regulator-boot-on;
  341. regulator-min-microvolt = <900000>;
  342. regulator-max-microvolt = <900000>;
  343. regulator-state-mem {
  344. regulator-on-in-suspend;
  345. regulator-suspend-microvolt = <900000>;
  346. };
  347. };
  348. vccio_acodec: LDO_REG4 {
  349. regulator-name = "vccio_acodec";
  350. regulator-always-on;
  351. regulator-boot-on;
  352. regulator-min-microvolt = <3300000>;
  353. regulator-max-microvolt = <3300000>;
  354. regulator-state-mem {
  355. regulator-off-in-suspend;
  356. };
  357. };
  358. vccio_sd: LDO_REG5 {
  359. regulator-name = "vccio_sd";
  360. regulator-min-microvolt = <1800000>;
  361. regulator-max-microvolt = <3300000>;
  362. regulator-state-mem {
  363. regulator-off-in-suspend;
  364. };
  365. };
  366. vcc3v3_pmu: LDO_REG6 {
  367. regulator-name = "vcc3v3_pmu";
  368. regulator-always-on;
  369. regulator-boot-on;
  370. regulator-min-microvolt = <3300000>;
  371. regulator-max-microvolt = <3300000>;
  372. regulator-state-mem {
  373. regulator-on-in-suspend;
  374. regulator-suspend-microvolt = <3300000>;
  375. };
  376. };
  377. vcca_1v8: LDO_REG7 {
  378. regulator-name = "vcca_1v8";
  379. regulator-always-on;
  380. regulator-boot-on;
  381. regulator-min-microvolt = <1800000>;
  382. regulator-max-microvolt = <1800000>;
  383. regulator-state-mem {
  384. regulator-off-in-suspend;
  385. };
  386. };
  387. vcca1v8_pmu: LDO_REG8 {
  388. regulator-name = "vcca1v8_pmu";
  389. regulator-always-on;
  390. regulator-boot-on;
  391. regulator-min-microvolt = <1800000>;
  392. regulator-max-microvolt = <1800000>;
  393. regulator-state-mem {
  394. regulator-on-in-suspend;
  395. regulator-suspend-microvolt = <1800000>;
  396. };
  397. };
  398. vcca1v8_image: LDO_REG9 {
  399. regulator-name = "vcca1v8_image";
  400. regulator-always-on;
  401. regulator-min-microvolt = <1800000>;
  402. regulator-max-microvolt = <1800000>;
  403. regulator-state-mem {
  404. regulator-off-in-suspend;
  405. };
  406. };
  407. vcc_3v3: SWITCH_REG1 {
  408. regulator-name = "vcc_3v3";
  409. regulator-always-on;
  410. regulator-boot-on;
  411. regulator-state-mem {
  412. regulator-off-in-suspend;
  413. };
  414. };
  415. vcc3v3_sd: SWITCH_REG2 {
  416. regulator-name = "vcc3v3_sd";
  417. regulator-always-on;
  418. regulator-state-mem {
  419. regulator-off-in-suspend;
  420. };
  421. };
  422. };
  423. };
  424. };
  425. &i2c3 {
  426. status = "okay";
  427. hym8563: rtc@51 {
  428. compatible = "haoyu,hym8563";
  429. reg = <0x51>;
  430. interrupt-parent = <&gpio0>;
  431. interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
  432. #clock-cells = <0>;
  433. clock-output-names = "rtcic_32kout";
  434. pinctrl-names = "default";
  435. pinctrl-0 = <&hym8563_int>;
  436. wakeup-source;
  437. };
  438. };
  439. &i2c5 {
  440. /* pin 3 (SDA) + 4 (SCL) of header con2 */
  441. status = "disabled";
  442. };
  443. &i2s0_8ch {
  444. /* hdmi sound */
  445. status = "okay";
  446. };
  447. &mdio0 {
  448. #address-cells = <1>;
  449. #size-cells = <0>;
  450. switch@0 {
  451. compatible = "mediatek,mt7531";
  452. reg = <0>;
  453. ports {
  454. #address-cells = <1>;
  455. #size-cells = <0>;
  456. port@1 {
  457. reg = <1>;
  458. label = "lan0";
  459. };
  460. port@2 {
  461. reg = <2>;
  462. label = "lan1";
  463. };
  464. port@3 {
  465. reg = <3>;
  466. label = "lan2";
  467. };
  468. port@4 {
  469. reg = <4>;
  470. label = "lan3";
  471. };
  472. port@5 {
  473. reg = <5>;
  474. label = "cpu";
  475. ethernet = <&gmac0>;
  476. phy-mode = "rgmii";
  477. fixed-link {
  478. speed = <1000>;
  479. full-duplex;
  480. pause;
  481. };
  482. };
  483. };
  484. };
  485. };
  486. &mdio1 {
  487. rgmii_phy1: ethernet-phy@0 {
  488. compatible = "ethernet-phy-ieee802.3-c22";
  489. reg = <0x0>;
  490. };
  491. };
  492. &pcie30phy {
  493. data-lanes = <1 2>;
  494. phy-supply = <&vcc3v3_pi6c_05>;
  495. status = "okay";
  496. };
  497. &pcie3x1 {
  498. /* M.2 slot */
  499. num-lanes = <1>;
  500. pinctrl-names = "default";
  501. pinctrl-0 = <&ngffpcie_reset_h>;
  502. reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
  503. vpcie3v3-supply = <&vcc3v3_ngff>;
  504. status = "okay";
  505. };
  506. &pcie3x2 {
  507. /* mPCIe slot */
  508. num-lanes = <1>;
  509. pinctrl-names = "default";
  510. pinctrl-0 = <&minipcie_reset_h>;
  511. reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
  512. vpcie3v3-supply = <&vcc3v3_minipcie>;
  513. status = "okay";
  514. };
  515. &pinctrl {
  516. leds {
  517. blue_led_pin: blue-led-pin {
  518. rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
  519. };
  520. green_led_pin: green-led-pin {
  521. rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
  522. };
  523. };
  524. hym8563 {
  525. hym8563_int: hym8563-int {
  526. rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
  527. };
  528. };
  529. pcie {
  530. minipcie_enable_h: minipcie-enable-h {
  531. rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
  532. };
  533. ngffpcie_enable_h: ngffpcie-enable-h {
  534. rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
  535. };
  536. minipcie_reset_h: minipcie-reset-h {
  537. rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
  538. };
  539. ngffpcie_reset_h: ngffpcie-reset-h {
  540. rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
  541. };
  542. };
  543. pmic {
  544. pmic_int: pmic_int {
  545. rockchip,pins =
  546. <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
  547. };
  548. };
  549. usb {
  550. vcc5v0_usb_host_en: vcc5v0_usb_host_en {
  551. rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
  552. };
  553. vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
  554. rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
  555. };
  556. };
  557. };
  558. &pmu_io_domains {
  559. pmuio1-supply = <&vcc3v3_pmu>;
  560. pmuio2-supply = <&vcc3v3_pmu>;
  561. vccio1-supply = <&vccio_acodec>;
  562. vccio3-supply = <&vccio_sd>;
  563. vccio4-supply = <&vcc_3v3>;
  564. vccio5-supply = <&vcc_3v3>;
  565. vccio6-supply = <&vcc_1v8>;
  566. vccio7-supply = <&vcc_3v3>;
  567. status = "okay";
  568. };
  569. &pwm8 {
  570. /* fan 5v - gnd - pwm */
  571. status = "okay";
  572. };
  573. &pwm10 {
  574. /* pin 7 of header con2 */
  575. status = "disabled";
  576. };
  577. &pwm11 {
  578. /* pin 15 of header con2 */
  579. status = "disabled";
  580. };
  581. &pwm12 {
  582. /* pin 21 of header con2 */
  583. /* shared with uart9 + spi3 */
  584. pinctrl-0 = <&pwm12m1_pins>;
  585. status = "disabled";
  586. };
  587. &pwm13 {
  588. /* pin 24 of header con2 */
  589. /* shared with uart9 */
  590. pinctrl-0 = <&pwm13m1_pins>;
  591. status = "disabled";
  592. };
  593. &pwm14 {
  594. /* pin 23 of header con2 */
  595. /* shared with spi3 */
  596. pinctrl-0 = <&pwm14m1_pins>;
  597. status = "disabled";
  598. };
  599. &pwm15 {
  600. /* pin 19 of header con2 */
  601. /* shared with spi3 */
  602. pinctrl-0 = <&pwm15m1_pins>;
  603. status = "disabled";
  604. };
  605. &saradc {
  606. vref-supply = <&vcca_1v8>;
  607. status = "okay";
  608. };
  609. &sata2 {
  610. status = "okay";
  611. };
  612. &sdhci {
  613. bus-width = <8>;
  614. max-frequency = <200000000>;
  615. non-removable;
  616. pinctrl-names = "default";
  617. pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
  618. status = "okay";
  619. };
  620. &sdmmc0 {
  621. bus-width = <4>;
  622. cap-sd-highspeed;
  623. cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
  624. disable-wp;
  625. pinctrl-names = "default";
  626. pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
  627. sd-uhs-sdr104;
  628. vmmc-supply = <&vcc3v3_sd>;
  629. vqmmc-supply = <&vccio_sd>;
  630. status = "okay";
  631. };
  632. &spi3 {
  633. /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */
  634. /* shared with pwm12/14/15 and uart9 */
  635. pinctrl-0 = <&spi3m1_pins>;
  636. status = "disabled";
  637. };
  638. &tsadc {
  639. rockchip,hw-tshut-mode = <1>;
  640. rockchip,hw-tshut-polarity = <0>;
  641. status = "okay";
  642. };
  643. &uart0 {
  644. /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
  645. status = "disabled";
  646. };
  647. &uart2 {
  648. /* debug-uart */
  649. status = "okay";
  650. };
  651. &uart7 {
  652. /* pin 11 (TX) + 13 (RX) of header con2 */
  653. pinctrl-0 = <&uart7m1_xfer>;
  654. status = "disabled";
  655. };
  656. &uart9 {
  657. /* pin 21 (TX) + 24 (RX) of header con2 */
  658. /* shared with pwm13 and pwm12/spi3 */
  659. pinctrl-0 = <&uart9m1_xfer>;
  660. status = "disabled";
  661. };
  662. &usb_host0_ehci {
  663. status = "okay";
  664. };
  665. &usb_host0_ohci {
  666. status = "okay";
  667. };
  668. &usb_host0_xhci {
  669. dr_mode = "host";
  670. status = "okay";
  671. };
  672. &usb_host1_ehci {
  673. status = "okay";
  674. };
  675. &usb_host1_ohci {
  676. status = "okay";
  677. };
  678. &usb_host1_xhci {
  679. status = "okay";
  680. };
  681. &usb2phy0 {
  682. status = "okay";
  683. };
  684. &usb2phy0_host {
  685. phy-supply = <&vcc5v0_usb_host>;
  686. status = "okay";
  687. };
  688. &usb2phy0_otg {
  689. phy-supply = <&vcc5v0_usb_otg>;
  690. status = "okay";
  691. };
  692. &usb2phy1 {
  693. /* USB for PCIe/M2 */
  694. status = "okay";
  695. };
  696. &usb2phy1_host {
  697. status = "okay";
  698. };
  699. &usb2phy1_otg {
  700. status = "okay";
  701. };
  702. &vop {
  703. assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
  704. assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
  705. status = "okay";
  706. };
  707. &vop_mmu {
  708. status = "okay";
  709. };
  710. &vp0 {
  711. vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
  712. reg = <ROCKCHIP_VOP2_EP_HDMI0>;
  713. remote-endpoint = <&hdmi_in_vp0>;
  714. };
  715. };