rk3399-roc-pc-mezzanine.dts 2.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
  4. * Copyright (c) 2019 Markus Reichl <[email protected]>
  5. */
  6. /dts-v1/;
  7. #include "rk3399-roc-pc.dtsi"
  8. / {
  9. model = "Firefly ROC-RK3399-PC Mezzanine Board";
  10. compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
  11. aliases {
  12. mmc2 = &sdio0;
  13. };
  14. /* MP8009 PoE PD */
  15. poe_12v: poe-12v {
  16. compatible = "regulator-fixed";
  17. regulator-name = "poe_12v";
  18. regulator-always-on;
  19. regulator-boot-on;
  20. regulator-min-microvolt = <12000000>;
  21. regulator-max-microvolt = <12000000>;
  22. };
  23. vcc3v3_ngff: vcc3v3-ngff {
  24. compatible = "regulator-fixed";
  25. regulator-name = "vcc3v3_ngff";
  26. enable-active-high;
  27. gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
  28. pinctrl-names = "default";
  29. pinctrl-0 = <&vcc3v3_ngff_en>;
  30. regulator-always-on;
  31. regulator-boot-on;
  32. regulator-min-microvolt = <3300000>;
  33. regulator-max-microvolt = <3300000>;
  34. vin-supply = <&sys_12v>;
  35. };
  36. vcc3v3_pcie: vcc3v3-pcie {
  37. compatible = "regulator-fixed";
  38. regulator-name = "vcc3v3_pcie";
  39. enable-active-high;
  40. gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&vcc3v3_pcie_en>;
  43. regulator-min-microvolt = <3300000>;
  44. regulator-max-microvolt = <3300000>;
  45. vin-supply = <&sys_12v>;
  46. };
  47. };
  48. &sys_12v {
  49. vin-supply = <&poe_12v>;
  50. };
  51. &pcie_phy {
  52. status = "okay";
  53. };
  54. &pcie0 {
  55. ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
  56. num-lanes = <4>;
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&pcie_perst>;
  59. vpcie3v3-supply = <&vcc3v3_pcie>;
  60. vpcie1v8-supply = <&vcc1v8_pmu>;
  61. vpcie0v9-supply = <&vcca_0v9>;
  62. status = "okay";
  63. };
  64. &pinctrl {
  65. ngff {
  66. vcc3v3_ngff_en: vcc3v3-ngff-en {
  67. rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
  68. };
  69. };
  70. pcie {
  71. vcc3v3_pcie_en: vcc3v3-pcie-en {
  72. rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
  73. };
  74. pcie_perst: pcie-perst {
  75. rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
  76. };
  77. };
  78. };
  79. &sdio0 {
  80. bus-width = <4>;
  81. cap-sd-highspeed;
  82. cap-sdio-irq;
  83. keep-power-in-suspend;
  84. mmc-pwrseq = <&sdio_pwrseq>;
  85. non-removable;
  86. pinctrl-names = "default";
  87. pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
  88. sd-uhs-sdr104;
  89. vmmc-supply = <&vcc3v3_ngff>;
  90. vqmmc-supply = <&vcc_1v8>;
  91. status = "okay";
  92. };
  93. &uart0 {
  94. pinctrl-names = "default";
  95. pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
  96. status = "okay";
  97. };