ulcb.dtsi 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the R-Car Gen3 ULCB board
  4. *
  5. * Copyright (C) 2016 Renesas Electronics Corp.
  6. * Copyright (C) 2016 Cogent Embedded, Inc.
  7. */
  8. /*
  9. * SSI-AK4613
  10. * aplay -D plughw:0,0 xxx.wav
  11. * arecord -D plughw:0,0 xxx.wav
  12. * SSI-HDMI
  13. * aplay -D plughw:0,1 xxx.wav
  14. */
  15. #include <dt-bindings/gpio/gpio.h>
  16. #include <dt-bindings/input/input.h>
  17. / {
  18. model = "Renesas R-Car Gen3 ULCB board";
  19. aliases {
  20. i2c0 = &i2c0;
  21. i2c1 = &i2c1;
  22. i2c2 = &i2c2;
  23. i2c3 = &i2c3;
  24. i2c4 = &i2c4;
  25. i2c5 = &i2c5;
  26. i2c6 = &i2c6;
  27. i2c7 = &i2c_dvfs;
  28. serial0 = &scif2;
  29. ethernet0 = &avb;
  30. mmc0 = &sdhi2;
  31. mmc1 = &sdhi0;
  32. };
  33. chosen {
  34. bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  35. stdout-path = "serial0:115200n8";
  36. };
  37. audio_clkout: audio-clkout {
  38. /*
  39. * This is same as <&rcar_sound 0>
  40. * but needed to avoid cs2000/rcar_sound probe dead-lock
  41. */
  42. compatible = "fixed-clock";
  43. #clock-cells = <0>;
  44. clock-frequency = <12288000>;
  45. };
  46. hdmi0-out {
  47. compatible = "hdmi-connector";
  48. type = "a";
  49. port {
  50. hdmi0_con: endpoint {
  51. remote-endpoint = <&rcar_dw_hdmi0_out>;
  52. };
  53. };
  54. };
  55. keyboard {
  56. compatible = "gpio-keys";
  57. key-1 {
  58. linux,code = <KEY_1>;
  59. label = "SW3";
  60. wakeup-source;
  61. debounce-interval = <20>;
  62. gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
  63. };
  64. };
  65. leds {
  66. compatible = "gpio-leds";
  67. led5 {
  68. gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
  69. };
  70. led6 {
  71. gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
  72. };
  73. };
  74. reg_1p8v: regulator-1p8v {
  75. compatible = "regulator-fixed";
  76. regulator-name = "fixed-1.8V";
  77. regulator-min-microvolt = <1800000>;
  78. regulator-max-microvolt = <1800000>;
  79. regulator-boot-on;
  80. regulator-always-on;
  81. };
  82. reg_3p3v: regulator-3p3v {
  83. compatible = "regulator-fixed";
  84. regulator-name = "fixed-3.3V";
  85. regulator-min-microvolt = <3300000>;
  86. regulator-max-microvolt = <3300000>;
  87. regulator-boot-on;
  88. regulator-always-on;
  89. };
  90. sound_card: sound {
  91. compatible = "audio-graph-card2";
  92. label = "rcar-sound";
  93. links = <&rsnd_port0 /* ak4613 */
  94. &rsnd_port1 /* HDMI0 */
  95. >;
  96. };
  97. vcc_sdhi0: regulator-vcc-sdhi0 {
  98. compatible = "regulator-fixed";
  99. regulator-name = "SDHI0 Vcc";
  100. regulator-min-microvolt = <3300000>;
  101. regulator-max-microvolt = <3300000>;
  102. gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  103. enable-active-high;
  104. };
  105. vccq_sdhi0: regulator-vccq-sdhi0 {
  106. compatible = "regulator-gpio";
  107. regulator-name = "SDHI0 VccQ";
  108. regulator-min-microvolt = <1800000>;
  109. regulator-max-microvolt = <3300000>;
  110. gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
  111. gpios-states = <1>;
  112. states = <3300000 1>, <1800000 0>;
  113. };
  114. x12_clk: x12 {
  115. compatible = "fixed-clock";
  116. #clock-cells = <0>;
  117. clock-frequency = <24576000>;
  118. };
  119. x23_clk: x23-clock {
  120. compatible = "fixed-clock";
  121. #clock-cells = <0>;
  122. clock-frequency = <25000000>;
  123. };
  124. };
  125. &a57_0 {
  126. cpu-supply = <&dvfs>;
  127. };
  128. &audio_clk_a {
  129. clock-frequency = <22579200>;
  130. };
  131. &avb {
  132. pinctrl-0 = <&avb_pins>;
  133. pinctrl-names = "default";
  134. phy-handle = <&phy0>;
  135. tx-internal-delay-ps = <2000>;
  136. status = "okay";
  137. phy0: ethernet-phy@0 {
  138. compatible = "ethernet-phy-id0022.1622",
  139. "ethernet-phy-ieee802.3-c22";
  140. rxc-skew-ps = <1500>;
  141. reg = <0>;
  142. interrupt-parent = <&gpio2>;
  143. interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  144. reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  145. };
  146. };
  147. &du {
  148. status = "okay";
  149. };
  150. &ehci1 {
  151. status = "okay";
  152. };
  153. &extal_clk {
  154. clock-frequency = <16666666>;
  155. };
  156. &extalr_clk {
  157. clock-frequency = <32768>;
  158. };
  159. &hdmi0 {
  160. status = "okay";
  161. ports {
  162. port@1 {
  163. reg = <1>;
  164. rcar_dw_hdmi0_out: endpoint {
  165. remote-endpoint = <&hdmi0_con>;
  166. };
  167. };
  168. port@2 {
  169. reg = <2>;
  170. dw_hdmi0_snd_in: endpoint {
  171. remote-endpoint = <&rsnd_for_hdmi>;
  172. };
  173. };
  174. };
  175. };
  176. &i2c2 {
  177. pinctrl-0 = <&i2c2_pins>;
  178. pinctrl-names = "default";
  179. status = "okay";
  180. clock-frequency = <100000>;
  181. ak4613: codec@10 {
  182. compatible = "asahi-kasei,ak4613";
  183. #sound-dai-cells = <0>;
  184. reg = <0x10>;
  185. clocks = <&rcar_sound 3>;
  186. asahi-kasei,in1-single-end;
  187. asahi-kasei,in2-single-end;
  188. asahi-kasei,out1-single-end;
  189. asahi-kasei,out2-single-end;
  190. asahi-kasei,out3-single-end;
  191. asahi-kasei,out4-single-end;
  192. asahi-kasei,out5-single-end;
  193. asahi-kasei,out6-single-end;
  194. port {
  195. ak4613_endpoint: endpoint {
  196. remote-endpoint = <&rsnd_for_ak4613>;
  197. };
  198. };
  199. };
  200. cs2000: clk-multiplier@4f {
  201. #clock-cells = <0>;
  202. compatible = "cirrus,cs2000-cp";
  203. reg = <0x4f>;
  204. clocks = <&audio_clkout>, <&x12_clk>;
  205. clock-names = "clk_in", "ref_clk";
  206. assigned-clocks = <&cs2000>;
  207. assigned-clock-rates = <24576000>; /* 1/1 divide */
  208. };
  209. };
  210. &i2c4 {
  211. status = "okay";
  212. clock-frequency = <400000>;
  213. versaclock5: clock-generator@6a {
  214. compatible = "idt,5p49v5925";
  215. reg = <0x6a>;
  216. #clock-cells = <1>;
  217. clocks = <&x23_clk>;
  218. clock-names = "xin";
  219. };
  220. };
  221. &i2c_dvfs {
  222. status = "okay";
  223. clock-frequency = <400000>;
  224. pmic: pmic@30 {
  225. pinctrl-0 = <&irq0_pins>;
  226. pinctrl-names = "default";
  227. compatible = "rohm,bd9571mwv";
  228. reg = <0x30>;
  229. interrupt-parent = <&intc_ex>;
  230. interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  231. interrupt-controller;
  232. #interrupt-cells = <2>;
  233. gpio-controller;
  234. #gpio-cells = <2>;
  235. rohm,ddr-backup-power = <0xf>;
  236. rohm,rstbmode-pulse;
  237. regulators {
  238. dvfs: dvfs {
  239. regulator-name = "dvfs";
  240. regulator-min-microvolt = <750000>;
  241. regulator-max-microvolt = <1030000>;
  242. regulator-boot-on;
  243. regulator-always-on;
  244. };
  245. };
  246. };
  247. };
  248. &ohci1 {
  249. status = "okay";
  250. };
  251. &pfc {
  252. pinctrl-0 = <&scif_clk_pins>;
  253. pinctrl-names = "default";
  254. avb_pins: avb {
  255. mux {
  256. groups = "avb_link", "avb_mdio", "avb_mii";
  257. function = "avb";
  258. };
  259. pins_mdio {
  260. groups = "avb_mdio";
  261. drive-strength = <24>;
  262. };
  263. pins_mii_tx {
  264. pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
  265. "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
  266. drive-strength = <12>;
  267. };
  268. };
  269. i2c2_pins: i2c2 {
  270. groups = "i2c2_a";
  271. function = "i2c2";
  272. };
  273. irq0_pins: irq0 {
  274. groups = "intc_ex_irq0";
  275. function = "intc_ex";
  276. };
  277. scif2_pins: scif2 {
  278. groups = "scif2_data_a";
  279. function = "scif2";
  280. };
  281. scif_clk_pins: scif_clk {
  282. groups = "scif_clk_a";
  283. function = "scif_clk";
  284. };
  285. sdhi0_pins: sd0 {
  286. groups = "sdhi0_data4", "sdhi0_ctrl";
  287. function = "sdhi0";
  288. power-source = <3300>;
  289. };
  290. sdhi0_pins_uhs: sd0_uhs {
  291. groups = "sdhi0_data4", "sdhi0_ctrl";
  292. function = "sdhi0";
  293. power-source = <1800>;
  294. };
  295. sdhi2_pins: sd2 {
  296. groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
  297. function = "sdhi2";
  298. power-source = <1800>;
  299. };
  300. sound_pins: sound {
  301. groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
  302. function = "ssi";
  303. };
  304. sound_clk_pins: sound-clk {
  305. groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
  306. "audio_clkout_a", "audio_clkout3_a";
  307. function = "audio_clk";
  308. };
  309. usb1_pins: usb1 {
  310. groups = "usb1";
  311. function = "usb1";
  312. };
  313. };
  314. &rcar_sound {
  315. pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
  316. pinctrl-names = "default";
  317. /* Single DAI */
  318. #sound-dai-cells = <0>;
  319. /* audio_clkout0/1/2/3 */
  320. #clock-cells = <1>;
  321. clock-frequency = <12288000 11289600>;
  322. status = "okay";
  323. /* update <audio_clk_b> to <cs2000> */
  324. clocks = <&cpg CPG_MOD 1005>,
  325. <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
  326. <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
  327. <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
  328. <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
  329. <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
  330. <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
  331. <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
  332. <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
  333. <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
  334. <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
  335. <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
  336. <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
  337. <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
  338. <&audio_clk_a>, <&cs2000>,
  339. <&audio_clk_c>,
  340. <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
  341. ports {
  342. #address-cells = <1>;
  343. #size-cells = <0>;
  344. rsnd_port0: port@0 {
  345. reg = <0>;
  346. rsnd_for_ak4613: endpoint {
  347. remote-endpoint = <&ak4613_endpoint>;
  348. bitclock-master;
  349. frame-master;
  350. playback = <&ssi0>, <&src0>, <&dvc0>;
  351. capture = <&ssi1>, <&src1>, <&dvc1>;
  352. };
  353. };
  354. rsnd_port1: port@1 {
  355. reg = <1>;
  356. rsnd_for_hdmi: endpoint {
  357. remote-endpoint = <&dw_hdmi0_snd_in>;
  358. bitclock-master;
  359. frame-master;
  360. playback = <&ssi2>;
  361. };
  362. };
  363. };
  364. };
  365. &rpc {
  366. /* Left disabled. To be enabled by firmware when unlocked. */
  367. flash@0 {
  368. compatible = "cypress,hyperflash", "cfi-flash";
  369. reg = <0>;
  370. partitions {
  371. compatible = "fixed-partitions";
  372. #address-cells = <1>;
  373. #size-cells = <1>;
  374. bootparam@0 {
  375. reg = <0x00000000 0x040000>;
  376. read-only;
  377. };
  378. bl2@40000 {
  379. reg = <0x00040000 0x140000>;
  380. read-only;
  381. };
  382. cert_header_sa6@180000 {
  383. reg = <0x00180000 0x040000>;
  384. read-only;
  385. };
  386. bl31@1c0000 {
  387. reg = <0x001c0000 0x040000>;
  388. read-only;
  389. };
  390. tee@200000 {
  391. reg = <0x00200000 0x440000>;
  392. read-only;
  393. };
  394. uboot@640000 {
  395. reg = <0x00640000 0x100000>;
  396. read-only;
  397. };
  398. dtb@740000 {
  399. reg = <0x00740000 0x080000>;
  400. };
  401. kernel@7c0000 {
  402. reg = <0x007c0000 0x1400000>;
  403. };
  404. user@1bc0000 {
  405. reg = <0x01bc0000 0x2440000>;
  406. };
  407. };
  408. };
  409. };
  410. &rwdt {
  411. timeout-sec = <60>;
  412. status = "okay";
  413. };
  414. &scif2 {
  415. pinctrl-0 = <&scif2_pins>;
  416. pinctrl-names = "default";
  417. status = "okay";
  418. };
  419. &scif_clk {
  420. clock-frequency = <14745600>;
  421. };
  422. &sdhi0 {
  423. pinctrl-0 = <&sdhi0_pins>;
  424. pinctrl-1 = <&sdhi0_pins_uhs>;
  425. pinctrl-names = "default", "state_uhs";
  426. vmmc-supply = <&vcc_sdhi0>;
  427. vqmmc-supply = <&vccq_sdhi0>;
  428. cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
  429. bus-width = <4>;
  430. sd-uhs-sdr50;
  431. sd-uhs-sdr104;
  432. status = "okay";
  433. };
  434. &sdhi2 {
  435. /* used for on-board 8bit eMMC */
  436. pinctrl-0 = <&sdhi2_pins>;
  437. pinctrl-1 = <&sdhi2_pins>;
  438. pinctrl-names = "default", "state_uhs";
  439. vmmc-supply = <&reg_3p3v>;
  440. vqmmc-supply = <&reg_1p8v>;
  441. bus-width = <8>;
  442. mmc-hs200-1_8v;
  443. mmc-hs400-1_8v;
  444. no-sd;
  445. no-sdio;
  446. non-removable;
  447. full-pwr-cycle-in-suspend;
  448. status = "okay";
  449. };
  450. &ssi1 {
  451. shared-pin;
  452. };
  453. &usb2_phy1 {
  454. pinctrl-0 = <&usb1_pins>;
  455. pinctrl-names = "default";
  456. status = "okay";
  457. };