r8a779g0.dtsi 15 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. /*
  3. * Device Tree Source for the R-Car V4H (R8A779G0) SoC
  4. *
  5. * Copyright (C) 2022 Renesas Electronics Corp.
  6. */
  7. #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. #include <dt-bindings/power/r8a779g0-sysc.h>
  10. / {
  11. compatible = "renesas,r8a779g0";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. cpus {
  15. #address-cells = <1>;
  16. #size-cells = <0>;
  17. a76_0: cpu@0 {
  18. compatible = "arm,cortex-a76";
  19. reg = <0>;
  20. device_type = "cpu";
  21. power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
  22. };
  23. };
  24. extal_clk: extal {
  25. compatible = "fixed-clock";
  26. #clock-cells = <0>;
  27. /* This value must be overridden by the board */
  28. clock-frequency = <0>;
  29. };
  30. extalr_clk: extalr {
  31. compatible = "fixed-clock";
  32. #clock-cells = <0>;
  33. /* This value must be overridden by the board */
  34. clock-frequency = <0>;
  35. };
  36. pmu_a76 {
  37. compatible = "arm,cortex-a76-pmu";
  38. interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  39. };
  40. /* External SCIF clock - to be overridden by boards that provide it */
  41. scif_clk: scif {
  42. compatible = "fixed-clock";
  43. #clock-cells = <0>;
  44. clock-frequency = <0>;
  45. };
  46. soc: soc {
  47. compatible = "simple-bus";
  48. interrupt-parent = <&gic>;
  49. #address-cells = <2>;
  50. #size-cells = <2>;
  51. ranges;
  52. rwdt: watchdog@e6020000 {
  53. compatible = "renesas,r8a779g0-wdt",
  54. "renesas,rcar-gen4-wdt";
  55. reg = <0 0xe6020000 0 0x0c>;
  56. interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
  57. clocks = <&cpg CPG_MOD 907>;
  58. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  59. resets = <&cpg 907>;
  60. status = "disabled";
  61. };
  62. pfc: pinctrl@e6050000 {
  63. compatible = "renesas,pfc-r8a779g0";
  64. reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
  65. <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
  66. <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
  67. <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
  68. <0 0xe6068000 0 0x16c>;
  69. };
  70. gpio0: gpio@e6050180 {
  71. compatible = "renesas,gpio-r8a779g0",
  72. "renesas,rcar-gen4-gpio";
  73. reg = <0 0xe6050180 0 0x54>;
  74. interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
  75. clocks = <&cpg CPG_MOD 915>;
  76. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  77. resets = <&cpg 915>;
  78. gpio-controller;
  79. #gpio-cells = <2>;
  80. gpio-ranges = <&pfc 0 0 19>;
  81. interrupt-controller;
  82. #interrupt-cells = <2>;
  83. };
  84. gpio1: gpio@e6050980 {
  85. compatible = "renesas,gpio-r8a779g0",
  86. "renesas,rcar-gen4-gpio";
  87. reg = <0 0xe6050980 0 0x54>;
  88. interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
  89. clocks = <&cpg CPG_MOD 915>;
  90. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  91. resets = <&cpg 915>;
  92. gpio-controller;
  93. #gpio-cells = <2>;
  94. gpio-ranges = <&pfc 0 32 29>;
  95. interrupt-controller;
  96. #interrupt-cells = <2>;
  97. };
  98. gpio2: gpio@e6058180 {
  99. compatible = "renesas,gpio-r8a779g0",
  100. "renesas,rcar-gen4-gpio";
  101. reg = <0 0xe6058180 0 0x54>;
  102. interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
  103. clocks = <&cpg CPG_MOD 916>;
  104. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  105. resets = <&cpg 916>;
  106. gpio-controller;
  107. #gpio-cells = <2>;
  108. gpio-ranges = <&pfc 0 64 20>;
  109. interrupt-controller;
  110. #interrupt-cells = <2>;
  111. };
  112. gpio3: gpio@e6058980 {
  113. compatible = "renesas,gpio-r8a779g0",
  114. "renesas,rcar-gen4-gpio";
  115. reg = <0 0xe6058980 0 0x54>;
  116. interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
  117. clocks = <&cpg CPG_MOD 916>;
  118. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  119. resets = <&cpg 916>;
  120. gpio-controller;
  121. #gpio-cells = <2>;
  122. gpio-ranges = <&pfc 0 96 30>;
  123. interrupt-controller;
  124. #interrupt-cells = <2>;
  125. };
  126. gpio4: gpio@e6060180 {
  127. compatible = "renesas,gpio-r8a779g0",
  128. "renesas,rcar-gen4-gpio";
  129. reg = <0 0xe6060180 0 0x54>;
  130. interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
  131. clocks = <&cpg CPG_MOD 917>;
  132. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  133. resets = <&cpg 917>;
  134. gpio-controller;
  135. #gpio-cells = <2>;
  136. gpio-ranges = <&pfc 0 128 25>;
  137. interrupt-controller;
  138. #interrupt-cells = <2>;
  139. };
  140. gpio5: gpio@e6060980 {
  141. compatible = "renesas,gpio-r8a779g0",
  142. "renesas,rcar-gen4-gpio";
  143. reg = <0 0xe6060980 0 0x54>;
  144. interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
  145. clocks = <&cpg CPG_MOD 917>;
  146. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  147. resets = <&cpg 917>;
  148. gpio-controller;
  149. #gpio-cells = <2>;
  150. gpio-ranges = <&pfc 0 160 21>;
  151. interrupt-controller;
  152. #interrupt-cells = <2>;
  153. };
  154. gpio6: gpio@e6061180 {
  155. compatible = "renesas,gpio-r8a779g0",
  156. "renesas,rcar-gen4-gpio";
  157. reg = <0 0xe6061180 0 0x54>;
  158. interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
  159. clocks = <&cpg CPG_MOD 917>;
  160. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  161. resets = <&cpg 917>;
  162. gpio-controller;
  163. #gpio-cells = <2>;
  164. gpio-ranges = <&pfc 0 192 21>;
  165. interrupt-controller;
  166. #interrupt-cells = <2>;
  167. };
  168. gpio7: gpio@e6061980 {
  169. compatible = "renesas,gpio-r8a779g0",
  170. "renesas,rcar-gen4-gpio";
  171. reg = <0 0xe6061980 0 0x54>;
  172. interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
  173. clocks = <&cpg CPG_MOD 917>;
  174. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  175. resets = <&cpg 917>;
  176. gpio-controller;
  177. #gpio-cells = <2>;
  178. gpio-ranges = <&pfc 0 224 21>;
  179. interrupt-controller;
  180. #interrupt-cells = <2>;
  181. };
  182. gpio8: gpio@e6068180 {
  183. compatible = "renesas,gpio-r8a779g0",
  184. "renesas,rcar-gen4-gpio";
  185. reg = <0 0xe6068180 0 0x54>;
  186. interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>;
  187. clocks = <&cpg CPG_MOD 918>;
  188. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  189. resets = <&cpg 918>;
  190. gpio-controller;
  191. #gpio-cells = <2>;
  192. gpio-ranges = <&pfc 0 256 14>;
  193. interrupt-controller;
  194. #interrupt-cells = <2>;
  195. };
  196. cpg: clock-controller@e6150000 {
  197. compatible = "renesas,r8a779g0-cpg-mssr";
  198. reg = <0 0xe6150000 0 0x4000>;
  199. clocks = <&extal_clk>, <&extalr_clk>;
  200. clock-names = "extal", "extalr";
  201. #clock-cells = <2>;
  202. #power-domain-cells = <0>;
  203. #reset-cells = <1>;
  204. };
  205. rst: reset-controller@e6160000 {
  206. compatible = "renesas,r8a779g0-rst";
  207. reg = <0 0xe6160000 0 0x4000>;
  208. };
  209. sysc: system-controller@e6180000 {
  210. compatible = "renesas,r8a779g0-sysc";
  211. reg = <0 0xe6180000 0 0x4000>;
  212. #power-domain-cells = <1>;
  213. };
  214. i2c0: i2c@e6500000 {
  215. compatible = "renesas,i2c-r8a779g0",
  216. "renesas,rcar-gen4-i2c";
  217. reg = <0 0xe6500000 0 0x40>;
  218. interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
  219. clocks = <&cpg CPG_MOD 518>;
  220. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  221. resets = <&cpg 518>;
  222. i2c-scl-internal-delay-ns = <110>;
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. status = "disabled";
  226. };
  227. i2c1: i2c@e6508000 {
  228. compatible = "renesas,i2c-r8a779g0",
  229. "renesas,rcar-gen4-i2c";
  230. reg = <0 0xe6508000 0 0x40>;
  231. interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
  232. clocks = <&cpg CPG_MOD 519>;
  233. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  234. resets = <&cpg 519>;
  235. i2c-scl-internal-delay-ns = <110>;
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. status = "disabled";
  239. };
  240. i2c2: i2c@e6510000 {
  241. compatible = "renesas,i2c-r8a779g0",
  242. "renesas,rcar-gen4-i2c";
  243. reg = <0 0xe6510000 0 0x40>;
  244. interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
  245. clocks = <&cpg CPG_MOD 520>;
  246. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  247. resets = <&cpg 520>;
  248. i2c-scl-internal-delay-ns = <110>;
  249. #address-cells = <1>;
  250. #size-cells = <0>;
  251. status = "disabled";
  252. };
  253. i2c3: i2c@e66d0000 {
  254. compatible = "renesas,i2c-r8a779g0",
  255. "renesas,rcar-gen4-i2c";
  256. reg = <0 0xe66d0000 0 0x40>;
  257. interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
  258. clocks = <&cpg CPG_MOD 521>;
  259. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  260. resets = <&cpg 521>;
  261. i2c-scl-internal-delay-ns = <110>;
  262. #address-cells = <1>;
  263. #size-cells = <0>;
  264. status = "disabled";
  265. };
  266. i2c4: i2c@e66d8000 {
  267. compatible = "renesas,i2c-r8a779g0",
  268. "renesas,rcar-gen4-i2c";
  269. reg = <0 0xe66d8000 0 0x40>;
  270. interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
  271. clocks = <&cpg CPG_MOD 522>;
  272. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  273. resets = <&cpg 522>;
  274. i2c-scl-internal-delay-ns = <110>;
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. status = "disabled";
  278. };
  279. i2c5: i2c@e66e0000 {
  280. compatible = "renesas,i2c-r8a779g0",
  281. "renesas,rcar-gen4-i2c";
  282. reg = <0 0xe66e0000 0 0x40>;
  283. interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
  284. clocks = <&cpg CPG_MOD 523>;
  285. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  286. resets = <&cpg 523>;
  287. i2c-scl-internal-delay-ns = <110>;
  288. #address-cells = <1>;
  289. #size-cells = <0>;
  290. status = "disabled";
  291. };
  292. hscif0: serial@e6540000 {
  293. compatible = "renesas,hscif-r8a779g0",
  294. "renesas,rcar-gen4-hscif",
  295. "renesas,hscif";
  296. reg = <0 0xe6540000 0 96>;
  297. interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
  298. clocks = <&cpg CPG_MOD 514>,
  299. <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
  300. <&scif_clk>;
  301. clock-names = "fck", "brg_int", "scif_clk";
  302. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  303. resets = <&cpg 514>;
  304. status = "disabled";
  305. };
  306. avb0: ethernet@e6800000 {
  307. compatible = "renesas,etheravb-r8a779g0",
  308. "renesas,etheravb-rcar-gen4";
  309. reg = <0 0xe6800000 0 0x800>;
  310. interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
  311. <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
  312. <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
  313. <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
  314. <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
  315. <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
  316. <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
  317. <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
  318. <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
  319. <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
  320. <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  321. <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
  322. <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
  323. <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
  324. <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
  325. <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
  326. <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
  327. <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
  328. <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
  329. <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
  330. <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
  331. <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
  332. <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
  333. <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
  334. <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
  335. interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
  336. "ch5", "ch6", "ch7", "ch8", "ch9",
  337. "ch10", "ch11", "ch12", "ch13",
  338. "ch14", "ch15", "ch16", "ch17",
  339. "ch18", "ch19", "ch20", "ch21",
  340. "ch22", "ch23", "ch24";
  341. clocks = <&cpg CPG_MOD 211>;
  342. clock-names = "fck";
  343. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  344. resets = <&cpg 211>;
  345. phy-mode = "rgmii";
  346. rx-internal-delay-ps = <0>;
  347. tx-internal-delay-ps = <0>;
  348. #address-cells = <1>;
  349. #size-cells = <0>;
  350. status = "disabled";
  351. };
  352. avb1: ethernet@e6810000 {
  353. compatible = "renesas,etheravb-r8a779g0",
  354. "renesas,etheravb-rcar-gen4";
  355. reg = <0 0xe6810000 0 0x800>;
  356. interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
  357. <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
  358. <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
  359. <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
  360. <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
  361. <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
  362. <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
  363. <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
  364. <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
  365. <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
  366. <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
  367. <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
  368. <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
  369. <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
  370. <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
  371. <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
  372. <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
  373. <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
  374. <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
  375. <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
  376. <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
  377. <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
  378. <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
  379. <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
  380. <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
  381. interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
  382. "ch5", "ch6", "ch7", "ch8", "ch9",
  383. "ch10", "ch11", "ch12", "ch13",
  384. "ch14", "ch15", "ch16", "ch17",
  385. "ch18", "ch19", "ch20", "ch21",
  386. "ch22", "ch23", "ch24";
  387. clocks = <&cpg CPG_MOD 212>;
  388. clock-names = "fck";
  389. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  390. resets = <&cpg 212>;
  391. phy-mode = "rgmii";
  392. rx-internal-delay-ps = <0>;
  393. tx-internal-delay-ps = <0>;
  394. #address-cells = <1>;
  395. #size-cells = <0>;
  396. status = "disabled";
  397. };
  398. avb2: ethernet@e6820000 {
  399. compatible = "renesas,etheravb-r8a779g0",
  400. "renesas,etheravb-rcar-gen4";
  401. reg = <0 0xe6820000 0 0x1000>;
  402. interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
  403. <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
  404. <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
  405. <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
  406. <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
  407. <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
  408. <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
  409. <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
  410. <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
  411. <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
  412. <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
  413. <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
  414. <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
  415. <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
  416. <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
  417. <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
  418. <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
  419. <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
  420. <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
  421. <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
  422. <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
  423. <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
  424. <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
  425. <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
  426. <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
  427. interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
  428. "ch5", "ch6", "ch7", "ch8", "ch9",
  429. "ch10", "ch11", "ch12", "ch13",
  430. "ch14", "ch15", "ch16", "ch17",
  431. "ch18", "ch19", "ch20", "ch21",
  432. "ch22", "ch23", "ch24";
  433. clocks = <&cpg CPG_MOD 213>;
  434. clock-names = "fck";
  435. power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  436. resets = <&cpg 213>;
  437. phy-mode = "rgmii";
  438. rx-internal-delay-ps = <0>;
  439. tx-internal-delay-ps = <0>;
  440. #address-cells = <1>;
  441. #size-cells = <0>;
  442. status = "disabled";
  443. };
  444. gic: interrupt-controller@f1000000 {
  445. compatible = "arm,gic-v3";
  446. #interrupt-cells = <3>;
  447. #address-cells = <0>;
  448. interrupt-controller;
  449. reg = <0x0 0xf1000000 0 0x20000>,
  450. <0x0 0xf1060000 0 0x110000>;
  451. interrupts = <GIC_PPI 9
  452. (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  453. };
  454. prr: chipid@fff00044 {
  455. compatible = "renesas,prr";
  456. reg = <0 0xfff00044 0 4>;
  457. };
  458. };
  459. timer {
  460. compatible = "arm,armv8-timer";
  461. interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  462. <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  463. <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  464. <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  465. };
  466. };