r8a77970-eagle.dts 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the Eagle board with R-Car V3M
  4. *
  5. * Copyright (C) 2016-2017 Renesas Electronics Corp.
  6. * Copyright (C) 2017 Cogent Embedded, Inc.
  7. */
  8. /dts-v1/;
  9. #include "r8a77970.dtsi"
  10. #include <dt-bindings/gpio/gpio.h>
  11. / {
  12. model = "Renesas Eagle board based on r8a77970";
  13. compatible = "renesas,eagle", "renesas,r8a77970";
  14. aliases {
  15. i2c0 = &i2c0;
  16. i2c1 = &i2c1;
  17. i2c2 = &i2c2;
  18. i2c3 = &i2c3;
  19. i2c4 = &i2c4;
  20. serial0 = &scif0;
  21. ethernet0 = &avb;
  22. };
  23. chosen {
  24. bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  25. stdout-path = "serial0:115200n8";
  26. };
  27. d3p3: regulator-fixed {
  28. compatible = "regulator-fixed";
  29. regulator-name = "fixed-3.3V";
  30. regulator-min-microvolt = <3300000>;
  31. regulator-max-microvolt = <3300000>;
  32. regulator-boot-on;
  33. regulator-always-on;
  34. };
  35. hdmi-out {
  36. compatible = "hdmi-connector";
  37. type = "a";
  38. port {
  39. hdmi_con_out: endpoint {
  40. remote-endpoint = <&adv7511_out>;
  41. };
  42. };
  43. };
  44. lvds-decoder {
  45. compatible = "thine,thc63lvd1024";
  46. vcc-supply = <&d3p3>;
  47. ports {
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. port@0 {
  51. reg = <0>;
  52. thc63lvd1024_in: endpoint {
  53. remote-endpoint = <&lvds0_out>;
  54. };
  55. };
  56. port@2 {
  57. reg = <2>;
  58. thc63lvd1024_out: endpoint {
  59. remote-endpoint = <&adv7511_in>;
  60. };
  61. };
  62. };
  63. };
  64. memory@48000000 {
  65. device_type = "memory";
  66. /* first 128MB is reserved for secure area. */
  67. reg = <0x0 0x48000000 0x0 0x38000000>;
  68. };
  69. x1_clk: x1-clock {
  70. compatible = "fixed-clock";
  71. #clock-cells = <0>;
  72. clock-frequency = <148500000>;
  73. };
  74. };
  75. &avb {
  76. pinctrl-0 = <&avb_pins>;
  77. pinctrl-names = "default";
  78. renesas,no-ether-link;
  79. phy-handle = <&phy0>;
  80. rx-internal-delay-ps = <1800>;
  81. tx-internal-delay-ps = <2000>;
  82. status = "okay";
  83. phy0: ethernet-phy@0 {
  84. compatible = "ethernet-phy-id0022.1622",
  85. "ethernet-phy-ieee802.3-c22";
  86. rxc-skew-ps = <1500>;
  87. reg = <0>;
  88. interrupt-parent = <&gpio1>;
  89. interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
  90. reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
  91. };
  92. };
  93. &canfd {
  94. pinctrl-0 = <&canfd0_pins>;
  95. pinctrl-names = "default";
  96. status = "okay";
  97. channel0 {
  98. status = "okay";
  99. };
  100. };
  101. &csi40 {
  102. status = "okay";
  103. ports {
  104. port@0 {
  105. csi40_in: endpoint {
  106. clock-lanes = <0>;
  107. data-lanes = <1 2 3 4>;
  108. remote-endpoint = <&max9286_out0>;
  109. };
  110. };
  111. };
  112. };
  113. &du {
  114. clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
  115. clock-names = "du.0", "dclkin.0";
  116. status = "okay";
  117. };
  118. &extal_clk {
  119. clock-frequency = <16666666>;
  120. };
  121. &extalr_clk {
  122. clock-frequency = <32768>;
  123. };
  124. &i2c0 {
  125. pinctrl-0 = <&i2c0_pins>;
  126. pinctrl-names = "default";
  127. status = "okay";
  128. clock-frequency = <400000>;
  129. io_expander: gpio@20 {
  130. compatible = "onnn,pca9654";
  131. reg = <0x20>;
  132. gpio-controller;
  133. #gpio-cells = <2>;
  134. };
  135. hdmi@39 {
  136. compatible = "adi,adv7511w";
  137. reg = <0x39>;
  138. interrupt-parent = <&gpio1>;
  139. interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
  140. adi,input-depth = <8>;
  141. adi,input-colorspace = "rgb";
  142. adi,input-clock = "1x";
  143. ports {
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. port@0 {
  147. reg = <0>;
  148. adv7511_in: endpoint {
  149. remote-endpoint = <&thc63lvd1024_out>;
  150. };
  151. };
  152. port@1 {
  153. reg = <1>;
  154. adv7511_out: endpoint {
  155. remote-endpoint = <&hdmi_con_out>;
  156. };
  157. };
  158. };
  159. };
  160. };
  161. &i2c3 {
  162. pinctrl-0 = <&i2c3_pins>;
  163. pinctrl-names = "default";
  164. status = "okay";
  165. clock-frequency = <400000>;
  166. gmsl0: gmsl-deserializer@48 {
  167. compatible = "maxim,max9286";
  168. reg = <0x48>;
  169. maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
  170. enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
  171. ports {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. port@0 {
  175. reg = <0>;
  176. };
  177. port@1 {
  178. reg = <1>;
  179. };
  180. port@2 {
  181. reg = <2>;
  182. };
  183. port@3 {
  184. reg = <3>;
  185. };
  186. port@4 {
  187. reg = <4>;
  188. max9286_out0: endpoint {
  189. clock-lanes = <0>;
  190. data-lanes = <1 2 3 4>;
  191. remote-endpoint = <&csi40_in>;
  192. };
  193. };
  194. };
  195. i2c-mux {
  196. #address-cells = <1>;
  197. #size-cells = <0>;
  198. i2c@0 {
  199. #address-cells = <1>;
  200. #size-cells = <0>;
  201. reg = <0>;
  202. status = "disabled";
  203. };
  204. i2c@1 {
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. reg = <1>;
  208. status = "disabled";
  209. };
  210. i2c@2 {
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. reg = <2>;
  214. status = "disabled";
  215. };
  216. i2c@3 {
  217. #address-cells = <1>;
  218. #size-cells = <0>;
  219. reg = <3>;
  220. status = "disabled";
  221. };
  222. };
  223. };
  224. };
  225. &lvds0 {
  226. status = "okay";
  227. ports {
  228. port@1 {
  229. lvds0_out: endpoint {
  230. remote-endpoint = <&thc63lvd1024_in>;
  231. };
  232. };
  233. };
  234. };
  235. &pfc {
  236. avb_pins: avb0 {
  237. groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
  238. function = "avb0";
  239. };
  240. canfd0_pins: canfd0 {
  241. groups = "canfd0_data_a";
  242. function = "canfd0";
  243. };
  244. i2c0_pins: i2c0 {
  245. groups = "i2c0";
  246. function = "i2c0";
  247. };
  248. i2c3_pins: i2c3 {
  249. groups = "i2c3_a";
  250. function = "i2c3";
  251. };
  252. qspi0_pins: qspi0 {
  253. groups = "qspi0_ctrl", "qspi0_data4";
  254. function = "qspi0";
  255. };
  256. scif0_pins: scif0 {
  257. groups = "scif0_data";
  258. function = "scif0";
  259. };
  260. };
  261. &rpc {
  262. pinctrl-0 = <&qspi0_pins>;
  263. pinctrl-names = "default";
  264. status = "okay";
  265. flash@0 {
  266. compatible = "spansion,s25fs512s", "jedec,spi-nor";
  267. reg = <0>;
  268. spi-max-frequency = <50000000>;
  269. spi-rx-bus-width = <4>;
  270. partitions {
  271. compatible = "fixed-partitions";
  272. #address-cells = <1>;
  273. #size-cells = <1>;
  274. bootparam@0 {
  275. reg = <0x00000000 0x040000>;
  276. read-only;
  277. };
  278. cr7@40000 {
  279. reg = <0x00040000 0x080000>;
  280. read-only;
  281. };
  282. cert_header_sa3@c0000 {
  283. reg = <0x000c0000 0x080000>;
  284. read-only;
  285. };
  286. bl2@140000 {
  287. reg = <0x00140000 0x040000>;
  288. read-only;
  289. };
  290. cert_header_sa6@180000 {
  291. reg = <0x00180000 0x040000>;
  292. read-only;
  293. };
  294. bl31@1c0000 {
  295. reg = <0x001c0000 0x460000>;
  296. read-only;
  297. };
  298. uboot@640000 {
  299. reg = <0x00640000 0x0c0000>;
  300. read-only;
  301. };
  302. uboot-env@700000 {
  303. reg = <0x00700000 0x040000>;
  304. read-only;
  305. };
  306. dtb@740000 {
  307. reg = <0x00740000 0x080000>;
  308. };
  309. kernel@7c0000 {
  310. reg = <0x007c0000 0x1400000>;
  311. };
  312. user@1bc0000 {
  313. reg = <0x01bc0000 0x2440000>;
  314. };
  315. };
  316. };
  317. };
  318. &rwdt {
  319. timeout-sec = <60>;
  320. status = "okay";
  321. };
  322. &scif0 {
  323. pinctrl-0 = <&scif0_pins>;
  324. pinctrl-names = "default";
  325. status = "okay";
  326. };