r8a774c0-cat874.dts 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
  4. *
  5. * Copyright (C) 2019 Renesas Electronics Corp.
  6. */
  7. /dts-v1/;
  8. #include "r8a774c0.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/display/tda998x.h>
  11. / {
  12. model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
  13. compatible = "si-linux,cat874", "renesas,r8a774c0";
  14. aliases {
  15. serial0 = &scif2;
  16. serial1 = &hscif2;
  17. mmc0 = &sdhi0;
  18. mmc1 = &sdhi3;
  19. };
  20. chosen {
  21. bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  22. stdout-path = "serial0:115200n8";
  23. };
  24. hdmi-out {
  25. compatible = "hdmi-connector";
  26. type = "a";
  27. port {
  28. hdmi_con_out: endpoint {
  29. remote-endpoint = <&tda19988_out>;
  30. };
  31. };
  32. };
  33. leds {
  34. compatible = "gpio-leds";
  35. led0 {
  36. gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
  37. label = "LED0";
  38. };
  39. led1 {
  40. gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
  41. label = "LED1";
  42. };
  43. led2 {
  44. gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
  45. label = "LED2";
  46. };
  47. led3 {
  48. gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
  49. label = "LED3";
  50. };
  51. };
  52. memory@48000000 {
  53. device_type = "memory";
  54. /* first 128MB is reserved for secure area. */
  55. reg = <0x0 0x48000000 0x0 0x78000000>;
  56. };
  57. reg_12p0v: regulator-12p0v {
  58. compatible = "regulator-fixed";
  59. regulator-name = "D12.0V";
  60. regulator-min-microvolt = <12000000>;
  61. regulator-max-microvolt = <12000000>;
  62. regulator-boot-on;
  63. regulator-always-on;
  64. };
  65. sound: sound {
  66. compatible = "simple-audio-card";
  67. simple-audio-card,name = "CAT874 HDMI sound";
  68. simple-audio-card,format = "i2s";
  69. simple-audio-card,bitclock-master = <&sndcpu>;
  70. simple-audio-card,frame-master = <&sndcpu>;
  71. sndcodec: simple-audio-card,codec {
  72. sound-dai = <&tda19988>;
  73. };
  74. sndcpu: simple-audio-card,cpu {
  75. sound-dai = <&rcar_sound>;
  76. };
  77. };
  78. vcc_sdhi0: regulator-vcc-sdhi0 {
  79. compatible = "regulator-fixed";
  80. regulator-name = "SDHI0 Vcc";
  81. regulator-min-microvolt = <3300000>;
  82. regulator-max-microvolt = <3300000>;
  83. regulator-always-on;
  84. regulator-boot-on;
  85. };
  86. vccq_sdhi0: regulator-vccq-sdhi0 {
  87. compatible = "regulator-gpio";
  88. regulator-name = "SDHI0 VccQ";
  89. regulator-min-microvolt = <1800000>;
  90. regulator-max-microvolt = <3300000>;
  91. gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  92. gpios-states = <1>;
  93. states = <3300000 1>, <1800000 0>;
  94. };
  95. wlan_en_reg: fixedregulator {
  96. compatible = "regulator-fixed";
  97. regulator-name = "wlan-en-regulator";
  98. regulator-min-microvolt = <1800000>;
  99. regulator-max-microvolt = <1800000>;
  100. startup-delay-us = <70000>;
  101. gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
  102. enable-active-high;
  103. };
  104. x13_clk: x13 {
  105. compatible = "fixed-clock";
  106. #clock-cells = <0>;
  107. clock-frequency = <74250000>;
  108. };
  109. connector {
  110. compatible = "usb-c-connector";
  111. label = "USB-C";
  112. data-role = "dual";
  113. ports {
  114. #address-cells = <1>;
  115. #size-cells = <0>;
  116. port@0 {
  117. reg = <0>;
  118. hs_ep: endpoint {
  119. remote-endpoint = <&usb3_hs_ep>;
  120. };
  121. };
  122. port@1 {
  123. reg = <1>;
  124. ss_ep: endpoint {
  125. remote-endpoint = <&hd3ss3220_in_ep>;
  126. };
  127. };
  128. };
  129. };
  130. };
  131. &audio_clk_a {
  132. clock-frequency = <22579200>;
  133. };
  134. &du {
  135. pinctrl-0 = <&du_pins>;
  136. pinctrl-names = "default";
  137. status = "okay";
  138. clocks = <&cpg CPG_MOD 724>,
  139. <&cpg CPG_MOD 723>,
  140. <&x13_clk>;
  141. clock-names = "du.0", "du.1", "dclkin.0";
  142. ports {
  143. port@0 {
  144. du_out_rgb: endpoint {
  145. remote-endpoint = <&tda19988_in>;
  146. };
  147. };
  148. };
  149. };
  150. &ehci0 {
  151. dr_mode = "host";
  152. status = "okay";
  153. };
  154. &extal_clk {
  155. clock-frequency = <48000000>;
  156. };
  157. &hscif2 {
  158. pinctrl-0 = <&hscif2_pins>;
  159. pinctrl-names = "default";
  160. uart-has-rtscts;
  161. status = "okay";
  162. bluetooth {
  163. compatible = "ti,wl1837-st";
  164. enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
  165. };
  166. };
  167. &i2c0 {
  168. status = "okay";
  169. clock-frequency = <100000>;
  170. hd3ss3220@47 {
  171. compatible = "ti,hd3ss3220";
  172. reg = <0x47>;
  173. interrupt-parent = <&gpio6>;
  174. interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  175. ports {
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. port@0 {
  179. reg = <0>;
  180. hd3ss3220_in_ep: endpoint {
  181. remote-endpoint = <&ss_ep>;
  182. };
  183. };
  184. port@1 {
  185. reg = <1>;
  186. hd3ss3220_out_ep: endpoint {
  187. remote-endpoint = <&usb3_role_switch>;
  188. };
  189. };
  190. };
  191. };
  192. tda19988: tda19988@70 {
  193. compatible = "nxp,tda998x";
  194. reg = <0x70>;
  195. interrupt-parent = <&gpio1>;
  196. interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
  197. video-ports = <0x234501>;
  198. #sound-dai-cells = <0>;
  199. audio-ports = <TDA998x_I2S 0x03>;
  200. clocks = <&rcar_sound 1>;
  201. ports {
  202. #address-cells = <1>;
  203. #size-cells = <0>;
  204. port@0 {
  205. reg = <0>;
  206. tda19988_in: endpoint {
  207. remote-endpoint = <&du_out_rgb>;
  208. };
  209. };
  210. port@1 {
  211. reg = <1>;
  212. tda19988_out: endpoint {
  213. remote-endpoint = <&hdmi_con_out>;
  214. };
  215. };
  216. };
  217. };
  218. };
  219. &i2c1 {
  220. pinctrl-0 = <&i2c1_pins>;
  221. pinctrl-names = "default";
  222. status = "okay";
  223. clock-frequency = <400000>;
  224. rtc@32 {
  225. compatible = "epson,rx8571";
  226. reg = <0x32>;
  227. };
  228. };
  229. &lvds0 {
  230. status = "okay";
  231. clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>;
  232. clock-names = "fck", "dclkin.0", "extal";
  233. };
  234. &ohci0 {
  235. dr_mode = "host";
  236. status = "okay";
  237. };
  238. &pcie_bus_clk {
  239. clock-frequency = <100000000>;
  240. };
  241. &pciec0 {
  242. /* Map all possible DDR as inbound ranges */
  243. dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
  244. };
  245. &pfc {
  246. du_pins: du {
  247. groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp",
  248. "du_clk_in_0";
  249. function = "du";
  250. };
  251. hscif2_pins: hscif2 {
  252. groups = "hscif2_data_a", "hscif2_ctrl_a";
  253. function = "hscif2";
  254. };
  255. i2c1_pins: i2c1 {
  256. groups = "i2c1_b";
  257. function = "i2c1";
  258. };
  259. scif2_pins: scif2 {
  260. groups = "scif2_data_a";
  261. function = "scif2";
  262. };
  263. sdhi0_pins: sd0 {
  264. groups = "sdhi0_data4", "sdhi0_ctrl";
  265. function = "sdhi0";
  266. power-source = <3300>;
  267. };
  268. sdhi0_pins_uhs: sd0_uhs {
  269. groups = "sdhi0_data4", "sdhi0_ctrl";
  270. function = "sdhi0";
  271. power-source = <1800>;
  272. };
  273. sdhi3_pins: sd3 {
  274. groups = "sdhi3_data4", "sdhi3_ctrl";
  275. function = "sdhi3";
  276. power-source = <1800>;
  277. };
  278. sound_clk_pins: sound_clk {
  279. groups = "audio_clkout1_a";
  280. function = "audio_clk";
  281. };
  282. sound_pins: sound {
  283. groups = "ssi01239_ctrl", "ssi0_data";
  284. function = "ssi";
  285. };
  286. usb30_pins: usb30 {
  287. groups = "usb30", "usb30_id";
  288. function = "usb30";
  289. };
  290. };
  291. &rcar_sound {
  292. pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
  293. pinctrl-names = "default";
  294. /* Single DAI */
  295. #sound-dai-cells = <0>;
  296. /* audio_clkout0/1/2/3 */
  297. #clock-cells = <1>;
  298. clock-frequency = <11289600>;
  299. status = "okay";
  300. rcar_sound,dai {
  301. dai0 {
  302. playback = <&ssi0>, <&src0>, <&dvc0>;
  303. };
  304. };
  305. };
  306. &rwdt {
  307. timeout-sec = <60>;
  308. status = "okay";
  309. };
  310. &scif2 {
  311. pinctrl-0 = <&scif2_pins>;
  312. pinctrl-names = "default";
  313. status = "okay";
  314. };
  315. &sdhi0 {
  316. pinctrl-0 = <&sdhi0_pins>;
  317. pinctrl-1 = <&sdhi0_pins_uhs>;
  318. pinctrl-names = "default", "state_uhs";
  319. vmmc-supply = <&vcc_sdhi0>;
  320. vqmmc-supply = <&vccq_sdhi0>;
  321. cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
  322. bus-width = <4>;
  323. sd-uhs-sdr50;
  324. sd-uhs-sdr104;
  325. status = "okay";
  326. };
  327. &sdhi3 {
  328. status = "okay";
  329. pinctrl-0 = <&sdhi3_pins>;
  330. pinctrl-names = "default";
  331. vmmc-supply = <&wlan_en_reg>;
  332. bus-width = <4>;
  333. non-removable;
  334. cap-power-off-card;
  335. keep-power-in-suspend;
  336. #address-cells = <1>;
  337. #size-cells = <0>;
  338. wlcore: wlcore@2 {
  339. compatible = "ti,wl1837";
  340. reg = <2>;
  341. interrupt-parent = <&gpio1>;
  342. interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
  343. };
  344. };
  345. &usb2_phy0 {
  346. renesas,no-otg-pins;
  347. status = "okay";
  348. };
  349. &usb3_peri0 {
  350. companion = <&xhci0>;
  351. status = "okay";
  352. usb-role-switch;
  353. ports {
  354. #address-cells = <1>;
  355. #size-cells = <0>;
  356. port@0 {
  357. reg = <0>;
  358. usb3_hs_ep: endpoint {
  359. remote-endpoint = <&hs_ep>;
  360. };
  361. };
  362. port@1 {
  363. reg = <1>;
  364. usb3_role_switch: endpoint {
  365. remote-endpoint = <&hd3ss3220_out_ep>;
  366. };
  367. };
  368. };
  369. };
  370. &xhci0 {
  371. pinctrl-0 = <&usb30_pins>;
  372. pinctrl-names = "default";
  373. status = "okay";
  374. };