beacon-renesom-som.dtsi 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2020, Compass Electronics Group, LLC
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/clock/versaclock.h>
  7. / {
  8. memory@48000000 {
  9. device_type = "memory";
  10. /* first 128MB is reserved for secure area. */
  11. reg = <0x0 0x48000000 0x0 0x78000000>;
  12. };
  13. osc_32k: osc_32k {
  14. compatible = "fixed-clock";
  15. #clock-cells = <0>;
  16. clock-frequency = <32768>;
  17. clock-output-names = "osc_32k";
  18. };
  19. reg_1p8v: regulator-1p8v {
  20. compatible = "regulator-fixed";
  21. regulator-name = "fixed-1.8V";
  22. regulator-min-microvolt = <1800000>;
  23. regulator-max-microvolt = <1800000>;
  24. regulator-boot-on;
  25. regulator-always-on;
  26. };
  27. reg_3p3v: regulator-3p3v {
  28. compatible = "regulator-fixed";
  29. regulator-name = "fixed-3.3V";
  30. regulator-min-microvolt = <3300000>;
  31. regulator-max-microvolt = <3300000>;
  32. regulator-boot-on;
  33. regulator-always-on;
  34. };
  35. wlan_pwrseq: wlan_pwrseq {
  36. compatible = "mmc-pwrseq-simple";
  37. reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
  38. clocks = <&osc_32k>;
  39. clock-names = "ext_clock";
  40. post-power-on-delay-ms = <80>;
  41. };
  42. };
  43. &avb {
  44. pinctrl-0 = <&avb_pins>;
  45. pinctrl-names = "default";
  46. phy-mode = "rgmii-rxid";
  47. phy-handle = <&phy0>;
  48. rx-internal-delay-ps = <1800>;
  49. tx-internal-delay-ps = <2000>;
  50. clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
  51. clock-names = "fck", "refclk";
  52. status = "okay";
  53. phy0: ethernet-phy@0 {
  54. compatible = "ethernet-phy-id004d.d074",
  55. "ethernet-phy-ieee802.3-c22";
  56. reg = <0>;
  57. interrupt-parent = <&gpio2>;
  58. interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  59. reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  60. };
  61. };
  62. &extal_clk {
  63. clock-frequency = <16666666>;
  64. };
  65. &extalr_clk {
  66. clock-frequency = <32768>;
  67. };
  68. &gpio6 {
  69. usb-hub-reset-hog {
  70. gpio-hog;
  71. gpios = <10 GPIO_ACTIVE_HIGH>;
  72. output-high;
  73. line-name = "usb-hub-reset";
  74. };
  75. };
  76. &hscif0 {
  77. pinctrl-0 = <&hscif0_pins>;
  78. pinctrl-names = "default";
  79. uart-has-rtscts;
  80. status = "okay";
  81. bluetooth {
  82. compatible = "brcm,bcm43438-bt";
  83. shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
  84. host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  85. device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
  86. clocks = <&osc_32k>;
  87. clock-names = "extclk";
  88. max-speed = <4000000>;
  89. };
  90. };
  91. &hscif2 {
  92. status = "okay";
  93. pinctrl-0 = <&hscif2_pins>;
  94. pinctrl-names = "default";
  95. };
  96. &i2c4 {
  97. status = "okay";
  98. clock-frequency = <100000>;
  99. pca9654: gpio@20 {
  100. compatible = "onnn,pca9654";
  101. reg = <0x20>;
  102. gpio-controller;
  103. #gpio-cells = <2>;
  104. gpio-line-names =
  105. "i2c4_20_0",
  106. "wl_reg_on",
  107. "bt_reg_on",
  108. "i2c4_20_3",
  109. "i2c4_20_4",
  110. "bt_dev_wake",
  111. "i2c4_20_6",
  112. "i2c4_20_7";
  113. };
  114. pca9654_lte: gpio@21 {
  115. compatible = "onnn,pca9654";
  116. reg = <0x21>;
  117. interrupt-parent = <&gpio5>;
  118. interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
  119. interrupt-controller;
  120. #interrupt-cells = <2>;
  121. gpio-controller;
  122. #gpio-cells = <2>;
  123. gpio-line-names =
  124. "i2c4_21_0",
  125. "zoe_pwr_on",
  126. "zoe_extint",
  127. "zoe_reset_n",
  128. "sara_reset",
  129. "i2c4_21_5",
  130. "sara_pwr_off",
  131. "sara_networking_status";
  132. };
  133. eeprom@50 {
  134. compatible = "microchip,24c64", "atmel,24c64";
  135. pagesize = <32>;
  136. read-only; /* Manufacturing EEPROM programmed at factory */
  137. reg = <0x50>;
  138. };
  139. rtc@51 {
  140. compatible = "nxp,pcf85263";
  141. reg = <0x51>;
  142. };
  143. versaclock5: versaclock_som@6a {
  144. compatible = "idt,5p49v6965";
  145. reg = <0x6a>;
  146. #clock-cells = <1>;
  147. clocks = <&x304_clk>;
  148. clock-names = "xin";
  149. /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
  150. assigned-clocks = <&versaclock5 1>,
  151. <&versaclock5 2>,
  152. <&versaclock5 3>,
  153. <&versaclock5 4>;
  154. assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
  155. OUT1 {
  156. idt,mode = <VC5_CMOS>;
  157. idt,voltage-microvolt = <1800000>;
  158. idt,slew-percent = <100>;
  159. };
  160. OUT2 {
  161. idt,mode = <VC5_CMOS>;
  162. idt,voltage-microvolt = <1800000>;
  163. idt,slew-percent = <100>;
  164. };
  165. OUT3 {
  166. idt,mode = <VC5_CMOS>;
  167. idt,voltage-microvolt = <1800000>;
  168. idt,slew-percent = <100>;
  169. };
  170. OUT4 {
  171. idt,mode = <VC5_CMOS>;
  172. idt,voltage-microvolt = <3300000>;
  173. idt,slew-percent = <100>;
  174. };
  175. };
  176. };
  177. &pfc {
  178. pinctrl-0 = <&scif_clk_pins>;
  179. pinctrl-names = "default";
  180. avb_pins: avb {
  181. mux {
  182. groups = "avb_link", "avb_mdio", "avb_mii";
  183. function = "avb";
  184. };
  185. pins_mdio {
  186. groups = "avb_mdio";
  187. drive-strength = <24>;
  188. };
  189. pins_mii_tx {
  190. pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
  191. "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
  192. drive-strength = <12>;
  193. };
  194. };
  195. scif2_pins: scif2 {
  196. groups = "scif2_data_a";
  197. function = "scif2";
  198. };
  199. hscif0_pins: hscif0 {
  200. groups = "hscif0_data", "hscif0_ctrl";
  201. function = "hscif0";
  202. };
  203. hscif1_pins: hscif1 {
  204. groups = "hscif1_data_a", "hscif1_ctrl_a";
  205. function = "hscif1";
  206. };
  207. hscif2_pins: hscif2 {
  208. groups = "hscif2_data_a";
  209. function = "hscif2";
  210. };
  211. scif0_pins: scif0 {
  212. groups = "scif0_data";
  213. function = "scif0";
  214. };
  215. scif5_pins: scif5 {
  216. groups = "scif5_data_a";
  217. function = "scif5";
  218. };
  219. scif_clk_pins: scif_clk {
  220. groups = "scif_clk_a";
  221. function = "scif_clk";
  222. };
  223. i2c0_pins: i2c0 {
  224. groups = "i2c0";
  225. function = "i2c0";
  226. };
  227. sdhi2_pins: sd2 {
  228. groups = "sdhi2_data4", "sdhi2_ctrl";
  229. function = "sdhi2";
  230. power-source = <1800>;
  231. };
  232. sdhi3_pins: sd3 {
  233. groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
  234. function = "sdhi3";
  235. power-source = <1800>;
  236. };
  237. };
  238. &scif_clk {
  239. clock-frequency = <14745600>;
  240. };
  241. &scif2 {
  242. pinctrl-0 = <&scif2_pins>;
  243. pinctrl-names = "default";
  244. status = "okay";
  245. };
  246. &sdhi2 {
  247. pinctrl-names = "default";
  248. pinctrl-0 = <&sdhi2_pins>;
  249. bus-width = <4>;
  250. vmmc-supply = <&reg_3p3v>;
  251. vqmmc-supply = <&reg_1p8v>;
  252. non-removable;
  253. cap-power-off-card;
  254. keep-power-in-suspend;
  255. mmc-pwrseq = <&wlan_pwrseq>;
  256. status = "okay";
  257. #address-cells = <1>;
  258. #size-cells = <0>;
  259. brcmf: bcrmf@1 {
  260. reg = <1>;
  261. compatible = "brcm,bcm4329-fmac";
  262. interrupt-parent = <&gpio1>;
  263. interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  264. interrupt-names = "host-wake";
  265. };
  266. };
  267. &sdhi3 {
  268. pinctrl-0 = <&sdhi3_pins>;
  269. pinctrl-1 = <&sdhi3_pins>;
  270. pinctrl-names = "default", "state_uhs";
  271. vmmc-supply = <&reg_3p3v>;
  272. vqmmc-supply = <&reg_1p8v>;
  273. bus-width = <8>;
  274. mmc-hs200-1_8v;
  275. no-sd;
  276. no-sdio;
  277. non-removable;
  278. fixed-emmc-driver-type = <1>;
  279. status = "okay";
  280. };
  281. &usb2_clksel {
  282. clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
  283. <&versaclock5 3>, <&usb3s0_clk>;
  284. status = "okay";
  285. };
  286. &usb3s0_clk {
  287. clock-frequency = <100000000>;
  288. };