rtd1296.dtsi 1.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
  2. /*
  3. * Realtek RTD1296 SoC
  4. *
  5. * Copyright (c) 2017-2019 Andreas Färber
  6. */
  7. #include "rtd129x.dtsi"
  8. / {
  9. compatible = "realtek,rtd1296";
  10. cpus {
  11. #address-cells = <2>;
  12. #size-cells = <0>;
  13. cpu0: cpu@0 {
  14. device_type = "cpu";
  15. compatible = "arm,cortex-a53";
  16. reg = <0x0 0x0>;
  17. next-level-cache = <&l2>;
  18. };
  19. cpu1: cpu@1 {
  20. device_type = "cpu";
  21. compatible = "arm,cortex-a53";
  22. reg = <0x0 0x1>;
  23. next-level-cache = <&l2>;
  24. };
  25. cpu2: cpu@2 {
  26. device_type = "cpu";
  27. compatible = "arm,cortex-a53";
  28. reg = <0x0 0x2>;
  29. next-level-cache = <&l2>;
  30. };
  31. cpu3: cpu@3 {
  32. device_type = "cpu";
  33. compatible = "arm,cortex-a53";
  34. reg = <0x0 0x3>;
  35. next-level-cache = <&l2>;
  36. };
  37. l2: l2-cache {
  38. compatible = "cache";
  39. };
  40. };
  41. timer {
  42. compatible = "arm,armv8-timer";
  43. interrupts = <GIC_PPI 13
  44. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  45. <GIC_PPI 14
  46. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  47. <GIC_PPI 11
  48. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  49. <GIC_PPI 10
  50. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  51. };
  52. };
  53. &arm_pmu {
  54. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  55. };