sdm845-lg-common.dtsi 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SDM845 LG G7 / V35 (judyln / judyp) common device tree
  4. *
  5. * Copyright (c) 2022, The Linux Foundation. All rights reserved.
  6. */
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
  9. #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
  10. #include "sdm845.dtsi"
  11. #include "pm8998.dtsi"
  12. #include "pmi8998.dtsi"
  13. /delete-node/ &adsp_mem;
  14. /delete-node/ &cdsp_mem;
  15. /delete-node/ &gpu_mem;
  16. /delete-node/ &ipa_fw_mem;
  17. /delete-node/ &mba_region;
  18. /delete-node/ &mpss_region;
  19. /delete-node/ &qseecom_mem;
  20. /delete-node/ &rmtfs_mem;
  21. /delete-node/ &slpi_mem;
  22. /delete-node/ &spss_mem;
  23. /delete-node/ &venus_mem;
  24. /delete-node/ &wlan_msa_mem;
  25. / {
  26. chosen {
  27. #address-cells = <2>;
  28. #size-cells = <2>;
  29. ranges;
  30. };
  31. reserved-memory {
  32. #address-cells = <2>;
  33. #size-cells = <2>;
  34. ranges;
  35. qseecom_mem: memory@b2000000 {
  36. reg = <0 0xb2000000 0 0x1800000>;
  37. no-map;
  38. };
  39. gpu_mem: memory@8c415000 {
  40. reg = <0 0x8c415000 0 0x2000>;
  41. no-map;
  42. };
  43. ipa_fw_mem: memory@8c400000 {
  44. reg = <0 0x8c400000 0 0x10000>;
  45. no-map;
  46. };
  47. adsp_mem: memory@8c500000 {
  48. reg = <0 0x8c500000 0 0x1e00000>;
  49. no-map;
  50. };
  51. wlan_msa_mem: memory@8e300000 {
  52. reg = <0 0x8e300000 0 0x100000>;
  53. no-map;
  54. };
  55. mpss_region: memory@8e400000 {
  56. reg = <0 0x8e400000 0 0x8900000>;
  57. no-map;
  58. };
  59. venus_mem: memory@96d00000 {
  60. reg = <0 0x96d00000 0 0x500000>;
  61. no-map;
  62. };
  63. cdsp_mem: memory@97200000 {
  64. reg = <0 0x97200000 0 0x800000>;
  65. no-map;
  66. };
  67. mba_region: memory@97a00000 {
  68. reg = <0 0x97a00000 0 0x200000>;
  69. no-map;
  70. };
  71. slpi_mem: memory@97c00000 {
  72. reg = <0 0x97c00000 0 0x1400000>;
  73. no-map;
  74. };
  75. spss_mem: memory@99000000 {
  76. reg = <0 0x99000000 0 0x100000>;
  77. no-map;
  78. };
  79. /* Framebuffer region */
  80. memory@9d400000 {
  81. reg = <0x0 0x9d400000 0x0 0x2400000>;
  82. no-map;
  83. };
  84. /* rmtfs lower guard */
  85. memory@f0800000 {
  86. reg = <0 0xf0800000 0 0x1000>;
  87. no-map;
  88. };
  89. rmtfs_mem: memory@f0801000 {
  90. compatible = "qcom,rmtfs-mem";
  91. reg = <0 0xf0801000 0 0x200000>;
  92. no-map;
  93. qcom,client-id = <1>;
  94. qcom,vmid = <15>;
  95. };
  96. /* rmtfs upper guard */
  97. memory@f0a01000 {
  98. reg = <0 0xf0a01000 0 0x1000>;
  99. no-map;
  100. };
  101. };
  102. gpio-keys {
  103. compatible = "gpio-keys";
  104. pinctrl-names = "default";
  105. pinctrl-0 = <&vol_up_pin_a>;
  106. label = "GPIO Buttons";
  107. key-vol-up {
  108. label = "Volume up";
  109. linux,code = <KEY_VOLUMEUP>;
  110. gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>;
  111. };
  112. };
  113. vph_pwr: vph-pwr-regulator {
  114. compatible = "regulator-fixed";
  115. regulator-name = "vph_pwr";
  116. regulator-min-microvolt = <3700000>;
  117. regulator-max-microvolt = <3700000>;
  118. };
  119. /*
  120. * Apparently RPMh does not provide support for PM8998 S4 because it
  121. * is always-on; model it as a fixed regulator.
  122. */
  123. vreg_s4a_1p8: pm8998-smps4-regulator {
  124. compatible = "regulator-fixed";
  125. regulator-name = "vreg_s4a_1p8";
  126. regulator-min-microvolt = <1800000>;
  127. regulator-max-microvolt = <1800000>;
  128. regulator-always-on;
  129. regulator-boot-on;
  130. vin-supply = <&vph_pwr>;
  131. };
  132. };
  133. &adsp_pas {
  134. status = "okay";
  135. };
  136. &apps_rsc {
  137. pm8998-rpmh-regulators {
  138. compatible = "qcom,pm8998-rpmh-regulators";
  139. qcom,pmic-id = "a";
  140. vdd-s1-supply = <&vph_pwr>;
  141. vdd-s2-supply = <&vph_pwr>;
  142. vdd-s3-supply = <&vph_pwr>;
  143. vdd-s4-supply = <&vph_pwr>;
  144. vdd-s5-supply = <&vph_pwr>;
  145. vdd-s6-supply = <&vph_pwr>;
  146. vdd-s7-supply = <&vph_pwr>;
  147. vdd-s8-supply = <&vph_pwr>;
  148. vdd-s9-supply = <&vph_pwr>;
  149. vdd-s10-supply = <&vph_pwr>;
  150. vdd-s11-supply = <&vph_pwr>;
  151. vdd-s12-supply = <&vph_pwr>;
  152. vdd-s13-supply = <&vph_pwr>;
  153. vdd-l1-l27-supply = <&vreg_s7a_1p025>;
  154. vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
  155. vdd-l3-l11-supply = <&vreg_s7a_1p025>;
  156. vdd-l4-l5-supply = <&vreg_s7a_1p025>;
  157. vdd-l6-supply = <&vph_pwr>;
  158. vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
  159. vdd-l9-supply = <&vreg_bob>;
  160. vdd-l10-l23-l25-supply = <&vreg_bob>;
  161. vdd-l13-l19-l21-supply = <&vreg_bob>;
  162. vdd-l16-l28-supply = <&vreg_bob>;
  163. vdd-l18-l22-supply = <&vreg_bob>;
  164. vdd-l20-l24-supply = <&vreg_bob>;
  165. vdd-l26-supply = <&vreg_s3a_1p35>;
  166. vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
  167. vreg_s2a_1p125: smps2 {
  168. regulator-min-microvolt = <1100000>;
  169. regulator-max-microvolt = <1100000>;
  170. };
  171. vreg_s3a_1p35: smps3 {
  172. regulator-min-microvolt = <1352000>;
  173. regulator-max-microvolt = <1352000>;
  174. };
  175. vreg_s5a_2p04: smps5 {
  176. regulator-min-microvolt = <1904000>;
  177. regulator-max-microvolt = <2040000>;
  178. };
  179. vreg_s7a_1p025: smps7 {
  180. regulator-min-microvolt = <900000>;
  181. regulator-max-microvolt = <1028000>;
  182. };
  183. vdd_qusb_hs0:
  184. vdda_hp_pcie_core:
  185. vdda_mipi_csi0_0p9:
  186. vdda_mipi_csi1_0p9:
  187. vdda_mipi_csi2_0p9:
  188. vdda_mipi_dsi0_pll:
  189. vdda_mipi_dsi1_pll:
  190. vdda_qlink_lv:
  191. vdda_qlink_lv_ck:
  192. vdda_qrefs_0p875:
  193. vdda_pcie_core:
  194. vdda_pll_cc_ebi01:
  195. vdda_pll_cc_ebi23:
  196. vdda_sp_sensor:
  197. vdda_ufs1_core:
  198. vdda_ufs2_core:
  199. vdda_usb1_ss_core:
  200. vdda_usb2_ss_core:
  201. vreg_l1a_0p875: ldo1 {
  202. regulator-min-microvolt = <880000>;
  203. regulator-max-microvolt = <880000>;
  204. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  205. };
  206. vddpx_10:
  207. vreg_l2a_1p2: ldo2 {
  208. regulator-min-microvolt = <1200000>;
  209. regulator-max-microvolt = <1200000>;
  210. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  211. regulator-always-on;
  212. };
  213. vreg_l3a_1p0: ldo3 {
  214. regulator-min-microvolt = <1000000>;
  215. regulator-max-microvolt = <1000000>;
  216. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  217. };
  218. vdd_wcss_cx:
  219. vdd_wcss_mx:
  220. vdda_wcss_pll:
  221. vreg_l5a_0p8: ldo5 {
  222. regulator-min-microvolt = <800000>;
  223. regulator-max-microvolt = <800000>;
  224. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  225. };
  226. vddpx_13:
  227. vreg_l6a_1p8: ldo6 {
  228. regulator-min-microvolt = <1856000>;
  229. regulator-max-microvolt = <1856000>;
  230. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  231. };
  232. vreg_l7a_1p8: ldo7 {
  233. regulator-min-microvolt = <1800000>;
  234. regulator-max-microvolt = <1800000>;
  235. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  236. };
  237. vreg_l8a_1p2: ldo8 {
  238. regulator-min-microvolt = <1200000>;
  239. regulator-max-microvolt = <1248000>;
  240. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  241. };
  242. vreg_l9a_1p8: ldo9 {
  243. regulator-min-microvolt = <1704000>;
  244. regulator-max-microvolt = <2928000>;
  245. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  246. };
  247. vreg_l10a_1p8: ldo10 {
  248. regulator-min-microvolt = <1704000>;
  249. regulator-max-microvolt = <2928000>;
  250. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  251. };
  252. vreg_l11a_1p0: ldo11 {
  253. regulator-min-microvolt = <1000000>;
  254. regulator-max-microvolt = <1048000>;
  255. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  256. };
  257. vdd_qfprom:
  258. vdd_qfprom_sp:
  259. vdda_apc1_cs_1p8:
  260. vdda_gfx_cs_1p8:
  261. vdda_qrefs_1p8:
  262. vdda_qusb_hs0_1p8:
  263. vddpx_11:
  264. vreg_l12a_1p8: ldo12 {
  265. regulator-min-microvolt = <1800000>;
  266. regulator-max-microvolt = <1800000>;
  267. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  268. };
  269. vddpx_2:
  270. vreg_l13a_2p95: ldo13 {
  271. regulator-min-microvolt = <1800000>;
  272. regulator-max-microvolt = <2960000>;
  273. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  274. };
  275. vreg_l14a_1p88: ldo14 {
  276. regulator-min-microvolt = <1800000>;
  277. regulator-max-microvolt = <1880000>;
  278. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  279. };
  280. vreg_l15a_1p8: ldo15 {
  281. regulator-min-microvolt = <1800000>;
  282. regulator-max-microvolt = <1800000>;
  283. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  284. };
  285. vreg_l17a_1p3: ldo17 {
  286. regulator-min-microvolt = <1304000>;
  287. regulator-max-microvolt = <1304000>;
  288. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  289. };
  290. vreg_l18a_2p7: ldo18 {
  291. regulator-min-microvolt = <2704000>;
  292. regulator-max-microvolt = <2960000>;
  293. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  294. };
  295. vreg_l20a_2p95: ldo20 {
  296. regulator-min-microvolt = <2704000>;
  297. regulator-max-microvolt = <2960000>;
  298. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  299. };
  300. vreg_l21a_2p95: ldo21 {
  301. regulator-min-microvolt = <2704000>;
  302. regulator-max-microvolt = <2960000>;
  303. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  304. };
  305. vreg_l22a_2p85: ldo22 {
  306. regulator-min-microvolt = <2800000>;
  307. regulator-max-microvolt = <2800000>;
  308. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  309. };
  310. vreg_l23a_3p3: ldo23 {
  311. regulator-min-microvolt = <3000000>;
  312. regulator-max-microvolt = <3312000>;
  313. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  314. };
  315. vdda_qusb_hs0_3p1:
  316. vreg_l24a_3p075: ldo24 {
  317. regulator-min-microvolt = <3088000>;
  318. regulator-max-microvolt = <3088000>;
  319. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  320. };
  321. vreg_l25a_3p3: ldo25 {
  322. regulator-min-microvolt = <3000000>;
  323. regulator-max-microvolt = <3312000>;
  324. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  325. };
  326. vdda_hp_pcie_1p2:
  327. vdda_hv_ebi0:
  328. vdda_hv_ebi1:
  329. vdda_hv_ebi2:
  330. vdda_hv_ebi3:
  331. vdda_mipi_csi_1p25:
  332. vdda_mipi_dsi0_1p2:
  333. vdda_mipi_dsi1_1p2:
  334. vdda_pcie_1p2:
  335. vdda_ufs1_1p2:
  336. vdda_ufs2_1p2:
  337. vdda_usb1_ss_1p2:
  338. vdda_usb2_ss_1p2:
  339. vreg_l26a_1p2: ldo26 {
  340. regulator-min-microvolt = <1200000>;
  341. regulator-max-microvolt = <1200000>;
  342. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  343. };
  344. vreg_l28a_3p0: ldo28 {
  345. regulator-min-microvolt = <1800000>;
  346. regulator-max-microvolt = <1800000>;
  347. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  348. };
  349. vreg_lvs1a_1p8: lvs1 {
  350. regulator-min-microvolt = <1800000>;
  351. regulator-max-microvolt = <1800000>;
  352. };
  353. vreg_lvs2a_1p8: lvs2 {
  354. regulator-min-microvolt = <1800000>;
  355. regulator-max-microvolt = <1800000>;
  356. };
  357. };
  358. pmi8998-rpmh-regulators {
  359. compatible = "qcom,pmi8998-rpmh-regulators";
  360. qcom,pmic-id = "b";
  361. vdd-bob-supply = <&vph_pwr>;
  362. vreg_bob: bob {
  363. regulator-min-microvolt = <3312000>;
  364. regulator-max-microvolt = <3600000>;
  365. regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
  366. regulator-allow-bypass;
  367. };
  368. };
  369. pm8005-rpmh-regulators {
  370. compatible = "qcom,pm8005-rpmh-regulators";
  371. qcom,pmic-id = "c";
  372. vdd-s1-supply = <&vph_pwr>;
  373. vdd-s2-supply = <&vph_pwr>;
  374. vdd-s3-supply = <&vph_pwr>;
  375. vdd-s4-supply = <&vph_pwr>;
  376. vreg_s3c_0p6: smps3 {
  377. regulator-min-microvolt = <600000>;
  378. regulator-max-microvolt = <600000>;
  379. };
  380. };
  381. };
  382. &cdsp_pas {
  383. status = "okay";
  384. };
  385. &dispcc {
  386. status = "disabled";
  387. };
  388. &gcc {
  389. protected-clocks = <GCC_QSPI_CORE_CLK>,
  390. <GCC_QSPI_CORE_CLK_SRC>,
  391. <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
  392. <GCC_LPASS_Q6_AXI_CLK>,
  393. <GCC_LPASS_SWAY_CLK>;
  394. };
  395. &gpu {
  396. status = "okay";
  397. zap-shader {
  398. memory-region = <&gpu_mem>;
  399. };
  400. };
  401. &ipa {
  402. status = "okay";
  403. modem-init;
  404. };
  405. &mss_pil {
  406. status = "okay";
  407. };
  408. &pm8998_pon {
  409. resin {
  410. compatible = "qcom,pm8941-resin";
  411. interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
  412. debounce = <15625>;
  413. bias-pull-up;
  414. linux,code = <KEY_VOLUMEDOWN>;
  415. };
  416. };
  417. &sdhc_2 {
  418. status = "okay";
  419. cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
  420. pinctrl-names = "default";
  421. pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>;
  422. vmmc-supply = <&vreg_l21a_2p95>;
  423. vqmmc-supply = <&vddpx_2>;
  424. };
  425. /*
  426. * UFS works partially and only with clk_ignore_unused.
  427. * Sometimes it crashes with I/O errors.
  428. */
  429. &ufs_mem_hc {
  430. status = "okay";
  431. reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
  432. vcc-supply = <&vreg_l20a_2p95>;
  433. vcc-max-microamp = <600000>;
  434. };
  435. &ufs_mem_phy {
  436. status = "okay";
  437. vdda-phy-supply = <&vdda_ufs1_core>;
  438. vdda-pll-supply = <&vdda_ufs1_1p2>;
  439. };
  440. &usb_1 {
  441. status = "okay";
  442. };
  443. &usb_1_dwc3 {
  444. /* TODO: these devices have usb id pin */
  445. dr_mode = "peripheral";
  446. };
  447. &usb_1_hsphy {
  448. status = "okay";
  449. vdd-supply = <&vdda_usb1_ss_core>;
  450. vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
  451. vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
  452. qcom,imp-res-offset-value = <8>;
  453. qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
  454. qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
  455. qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
  456. };
  457. &usb_1_qmpphy {
  458. status = "okay";
  459. vdda-phy-supply = <&vdda_usb1_ss_1p2>;
  460. vdda-pll-supply = <&vdda_usb1_ss_core>;
  461. };
  462. /* PINCTRL - additions to nodes defined in sdm845.dtsi */
  463. &tlmm {
  464. gpio-reserved-ranges = <28 4>, <81 4>;
  465. sdc2_clk: sdc2-clk {
  466. pinconf {
  467. pins = "sdc2_clk";
  468. bias-disable;
  469. /*
  470. * It seems that mmc_test reports errors if drive
  471. * strength is not 16 on clk, cmd, and data pins.
  472. *
  473. * TODO: copy-pasted from mtp, try other values
  474. * on these devices.
  475. */
  476. drive-strength = <16>;
  477. };
  478. };
  479. sdc2_cmd: sdc2-cmd {
  480. pinconf {
  481. pins = "sdc2_cmd";
  482. bias-pull-up;
  483. drive-strength = <16>;
  484. };
  485. };
  486. sdc2_data: sdc2-data {
  487. pinconf {
  488. pins = "sdc2_data";
  489. bias-pull-up;
  490. drive-strength = <16>;
  491. };
  492. };
  493. sd_card_det_n: sd-card-det-n {
  494. pinmux {
  495. pins = "gpio126";
  496. function = "gpio";
  497. };
  498. pinconf {
  499. pins = "gpio126";
  500. bias-pull-up;
  501. };
  502. };
  503. };
  504. &pm8998_gpio {
  505. vol_up_pin_a: vol-up-active-pins {
  506. pins = "gpio6";
  507. function = "normal";
  508. input-enable;
  509. bias-pull-up;
  510. qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
  511. };
  512. };