sdm845-cheza.dtsi 29 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Google Cheza device tree source (common between revisions)
  4. *
  5. * Copyright 2018 Google LLC.
  6. */
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
  9. #include "sdm845.dtsi"
  10. /* PMICs depend on spmi_bus label and so must come after SoC */
  11. #include "pm8005.dtsi"
  12. #include "pm8998.dtsi"
  13. / {
  14. aliases {
  15. bluetooth0 = &bluetooth;
  16. hsuart0 = &uart6;
  17. serial0 = &uart9;
  18. wifi0 = &wifi;
  19. };
  20. chosen {
  21. stdout-path = "serial0:115200n8";
  22. };
  23. backlight: backlight {
  24. compatible = "pwm-backlight";
  25. pwms = <&cros_ec_pwm 0>;
  26. enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
  27. power-supply = <&ppvar_sys>;
  28. pinctrl-names = "default";
  29. pinctrl-0 = <&ap_edp_bklten>;
  30. };
  31. /* FIXED REGULATORS - parents above children */
  32. /* This is the top level supply and variable voltage */
  33. ppvar_sys: ppvar-sys-regulator {
  34. compatible = "regulator-fixed";
  35. regulator-name = "ppvar_sys";
  36. regulator-always-on;
  37. regulator-boot-on;
  38. };
  39. /* This divides ppvar_sys by 2, so voltage is variable */
  40. src_vph_pwr: src-vph-pwr-regulator {
  41. compatible = "regulator-fixed";
  42. regulator-name = "src_vph_pwr";
  43. /* EC turns on with switchcap_on_l; always on for AP */
  44. regulator-always-on;
  45. regulator-boot-on;
  46. vin-supply = <&ppvar_sys>;
  47. };
  48. pp5000_a: pp5000-a-regulator {
  49. compatible = "regulator-fixed";
  50. regulator-name = "pp5000_a";
  51. /* EC turns on with en_pp5000_a; always on for AP */
  52. regulator-always-on;
  53. regulator-boot-on;
  54. regulator-min-microvolt = <5000000>;
  55. regulator-max-microvolt = <5000000>;
  56. vin-supply = <&ppvar_sys>;
  57. };
  58. src_vreg_bob: src-vreg-bob-regulator {
  59. compatible = "regulator-fixed";
  60. regulator-name = "src_vreg_bob";
  61. /* EC turns on with vbob_en; always on for AP */
  62. regulator-always-on;
  63. regulator-boot-on;
  64. regulator-min-microvolt = <3600000>;
  65. regulator-max-microvolt = <3600000>;
  66. vin-supply = <&ppvar_sys>;
  67. };
  68. pp3300_dx_edp: pp3300-dx-edp-regulator {
  69. compatible = "regulator-fixed";
  70. regulator-name = "pp3300_dx_edp";
  71. regulator-min-microvolt = <3300000>;
  72. regulator-max-microvolt = <3300000>;
  73. gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
  74. enable-active-high;
  75. pinctrl-names = "default";
  76. pinctrl-0 = <&en_pp3300_dx_edp>;
  77. };
  78. /*
  79. * Apparently RPMh does not provide support for PM8998 S4 because it
  80. * is always-on; model it as a fixed regulator.
  81. */
  82. src_pp1800_s4a: pm8998-smps4 {
  83. compatible = "regulator-fixed";
  84. regulator-name = "src_pp1800_s4a";
  85. regulator-min-microvolt = <1800000>;
  86. regulator-max-microvolt = <1800000>;
  87. regulator-always-on;
  88. regulator-boot-on;
  89. vin-supply = <&src_vph_pwr>;
  90. };
  91. /* BOARD-SPECIFIC TOP LEVEL NODES */
  92. gpio-keys {
  93. compatible = "gpio-keys";
  94. pinctrl-names = "default";
  95. pinctrl-0 = <&pen_eject_odl>;
  96. switch-pen-insert {
  97. label = "Pen Insert";
  98. /* Insert = low, eject = high */
  99. gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
  100. linux,code = <SW_PEN_INSERTED>;
  101. linux,input-type = <EV_SW>;
  102. wakeup-source;
  103. };
  104. };
  105. panel: panel {
  106. compatible = "innolux,p120zdg-bf1";
  107. power-supply = <&pp3300_dx_edp>;
  108. backlight = <&backlight>;
  109. no-hpd;
  110. ports {
  111. panel_in: port {
  112. panel_in_edp: endpoint {
  113. remote-endpoint = <&sn65dsi86_out>;
  114. };
  115. };
  116. };
  117. };
  118. };
  119. &cpufreq_hw {
  120. /delete-property/ interrupts-extended; /* reference to lmh_cluster[01] */
  121. };
  122. &psci {
  123. /delete-node/ cpu0;
  124. /delete-node/ cpu1;
  125. /delete-node/ cpu2;
  126. /delete-node/ cpu3;
  127. /delete-node/ cpu4;
  128. /delete-node/ cpu5;
  129. /delete-node/ cpu6;
  130. /delete-node/ cpu7;
  131. /delete-node/ cpu-cluster0;
  132. };
  133. &cpus {
  134. /delete-node/ domain-idle-states;
  135. };
  136. &cpu_idle_states {
  137. LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
  138. compatible = "arm,idle-state";
  139. idle-state-name = "little-power-down";
  140. arm,psci-suspend-param = <0x40000003>;
  141. entry-latency-us = <350>;
  142. exit-latency-us = <461>;
  143. min-residency-us = <1890>;
  144. local-timer-stop;
  145. };
  146. LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
  147. compatible = "arm,idle-state";
  148. idle-state-name = "little-rail-power-down";
  149. arm,psci-suspend-param = <0x40000004>;
  150. entry-latency-us = <360>;
  151. exit-latency-us = <531>;
  152. min-residency-us = <3934>;
  153. local-timer-stop;
  154. };
  155. BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
  156. compatible = "arm,idle-state";
  157. idle-state-name = "big-power-down";
  158. arm,psci-suspend-param = <0x40000003>;
  159. entry-latency-us = <264>;
  160. exit-latency-us = <621>;
  161. min-residency-us = <952>;
  162. local-timer-stop;
  163. };
  164. BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
  165. compatible = "arm,idle-state";
  166. idle-state-name = "big-rail-power-down";
  167. arm,psci-suspend-param = <0x40000004>;
  168. entry-latency-us = <702>;
  169. exit-latency-us = <1061>;
  170. min-residency-us = <4488>;
  171. local-timer-stop;
  172. };
  173. CLUSTER_SLEEP_0: cluster-sleep-0 {
  174. compatible = "arm,idle-state";
  175. idle-state-name = "cluster-power-down";
  176. arm,psci-suspend-param = <0x400000F4>;
  177. entry-latency-us = <3263>;
  178. exit-latency-us = <6562>;
  179. min-residency-us = <9987>;
  180. local-timer-stop;
  181. };
  182. };
  183. &CPU0 {
  184. /delete-property/ power-domains;
  185. /delete-property/ power-domain-names;
  186. cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  187. &LITTLE_CPU_SLEEP_1
  188. &CLUSTER_SLEEP_0>;
  189. };
  190. &CPU1 {
  191. /delete-property/ power-domains;
  192. /delete-property/ power-domain-names;
  193. cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  194. &LITTLE_CPU_SLEEP_1
  195. &CLUSTER_SLEEP_0>;
  196. };
  197. &CPU2 {
  198. /delete-property/ power-domains;
  199. /delete-property/ power-domain-names;
  200. cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  201. &LITTLE_CPU_SLEEP_1
  202. &CLUSTER_SLEEP_0>;
  203. };
  204. &CPU3 {
  205. /delete-property/ power-domains;
  206. /delete-property/ power-domain-names;
  207. cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  208. &LITTLE_CPU_SLEEP_1
  209. &CLUSTER_SLEEP_0>;
  210. };
  211. &CPU4 {
  212. /delete-property/ power-domains;
  213. /delete-property/ power-domain-names;
  214. cpu-idle-states = <&BIG_CPU_SLEEP_0
  215. &BIG_CPU_SLEEP_1
  216. &CLUSTER_SLEEP_0>;
  217. };
  218. &CPU5 {
  219. /delete-property/ power-domains;
  220. /delete-property/ power-domain-names;
  221. cpu-idle-states = <&BIG_CPU_SLEEP_0
  222. &BIG_CPU_SLEEP_1
  223. &CLUSTER_SLEEP_0>;
  224. };
  225. &CPU6 {
  226. /delete-property/ power-domains;
  227. /delete-property/ power-domain-names;
  228. cpu-idle-states = <&BIG_CPU_SLEEP_0
  229. &BIG_CPU_SLEEP_1
  230. &CLUSTER_SLEEP_0>;
  231. };
  232. &CPU7 {
  233. /delete-property/ power-domains;
  234. /delete-property/ power-domain-names;
  235. cpu-idle-states = <&BIG_CPU_SLEEP_0
  236. &BIG_CPU_SLEEP_1
  237. &CLUSTER_SLEEP_0>;
  238. };
  239. &lmh_cluster0 {
  240. status = "disabled";
  241. };
  242. &lmh_cluster1 {
  243. status = "disabled";
  244. };
  245. /*
  246. * Reserved memory changes
  247. *
  248. * Putting this all together (out of order with the rest of the file) to keep
  249. * all modifications to the memory map (from sdm845.dtsi) in one place.
  250. */
  251. /*
  252. * Our mpss_region is 8MB bigger than the default one and that conflicts
  253. * with venus_mem and cdsp_mem.
  254. *
  255. * For venus_mem we'll delete and re-create at a different address.
  256. *
  257. * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but
  258. * that also means we need to delete cdsp_pas.
  259. */
  260. /delete-node/ &venus_mem;
  261. /delete-node/ &cdsp_mem;
  262. /delete-node/ &cdsp_pas;
  263. /delete-node/ &gpu_mem;
  264. /* Increase the size from 120 MB to 128 MB */
  265. &mpss_region {
  266. reg = <0 0x8e000000 0 0x8000000>;
  267. };
  268. /* Increase the size from 2MB to 8MB */
  269. &rmtfs_mem {
  270. reg = <0 0x88f00000 0 0x800000>;
  271. };
  272. / {
  273. reserved-memory {
  274. venus_mem: memory@96000000 {
  275. reg = <0 0x96000000 0 0x500000>;
  276. no-map;
  277. };
  278. };
  279. };
  280. &qspi {
  281. status = "okay";
  282. pinctrl-names = "default";
  283. pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
  284. flash@0 {
  285. compatible = "jedec,spi-nor";
  286. reg = <0>;
  287. /*
  288. * In theory chip supports up to 104 MHz and controller up
  289. * to 80 MHz, but above 25 MHz wasn't reliable so we'll use
  290. * that for now. b:117440651
  291. */
  292. spi-max-frequency = <25000000>;
  293. spi-tx-bus-width = <2>;
  294. spi-rx-bus-width = <2>;
  295. };
  296. };
  297. &apps_rsc {
  298. pm8998-rpmh-regulators {
  299. compatible = "qcom,pm8998-rpmh-regulators";
  300. qcom,pmic-id = "a";
  301. vdd-s1-supply = <&src_vph_pwr>;
  302. vdd-s2-supply = <&src_vph_pwr>;
  303. vdd-s3-supply = <&src_vph_pwr>;
  304. vdd-s4-supply = <&src_vph_pwr>;
  305. vdd-s5-supply = <&src_vph_pwr>;
  306. vdd-s6-supply = <&src_vph_pwr>;
  307. vdd-s7-supply = <&src_vph_pwr>;
  308. vdd-s8-supply = <&src_vph_pwr>;
  309. vdd-s9-supply = <&src_vph_pwr>;
  310. vdd-s10-supply = <&src_vph_pwr>;
  311. vdd-s11-supply = <&src_vph_pwr>;
  312. vdd-s12-supply = <&src_vph_pwr>;
  313. vdd-s13-supply = <&src_vph_pwr>;
  314. vdd-l1-l27-supply = <&src_pp1025_s7a>;
  315. vdd-l2-l8-l17-supply = <&src_pp1350_s3a>;
  316. vdd-l3-l11-supply = <&src_pp1025_s7a>;
  317. vdd-l4-l5-supply = <&src_pp1025_s7a>;
  318. vdd-l6-supply = <&src_vph_pwr>;
  319. vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>;
  320. vdd-l9-supply = <&src_pp2040_s5a>;
  321. vdd-l10-l23-l25-supply = <&src_vreg_bob>;
  322. vdd-l13-l19-l21-supply = <&src_vreg_bob>;
  323. vdd-l16-l28-supply = <&src_vreg_bob>;
  324. vdd-l18-l22-supply = <&src_vreg_bob>;
  325. vdd-l20-l24-supply = <&src_vreg_bob>;
  326. vdd-l26-supply = <&src_pp1350_s3a>;
  327. vin-lvs-1-2-supply = <&src_pp1800_s4a>;
  328. src_pp1125_s2a: smps2 {
  329. regulator-min-microvolt = <1100000>;
  330. regulator-max-microvolt = <1100000>;
  331. };
  332. src_pp1350_s3a: smps3 {
  333. regulator-min-microvolt = <1352000>;
  334. regulator-max-microvolt = <1352000>;
  335. };
  336. src_pp2040_s5a: smps5 {
  337. regulator-min-microvolt = <1904000>;
  338. regulator-max-microvolt = <2040000>;
  339. };
  340. src_pp1025_s7a: smps7 {
  341. regulator-min-microvolt = <900000>;
  342. regulator-max-microvolt = <1028000>;
  343. };
  344. vdd_qusb_hs0:
  345. vdda_hp_pcie_core:
  346. vdda_mipi_csi0_0p9:
  347. vdda_mipi_csi1_0p9:
  348. vdda_mipi_csi2_0p9:
  349. vdda_mipi_dsi0_pll:
  350. vdda_mipi_dsi1_pll:
  351. vdda_qlink_lv:
  352. vdda_qlink_lv_ck:
  353. vdda_qrefs_0p875:
  354. vdda_pcie_core:
  355. vdda_pll_cc_ebi01:
  356. vdda_pll_cc_ebi23:
  357. vdda_sp_sensor:
  358. vdda_ufs1_core:
  359. vdda_ufs2_core:
  360. vdda_usb1_ss_core:
  361. vdda_usb2_ss_core:
  362. src_pp875_l1a: ldo1 {
  363. regulator-min-microvolt = <880000>;
  364. regulator-max-microvolt = <880000>;
  365. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  366. };
  367. vddpx_10:
  368. src_pp1200_l2a: ldo2 {
  369. regulator-min-microvolt = <1200000>;
  370. regulator-max-microvolt = <1200000>;
  371. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  372. /* TODO: why??? */
  373. regulator-always-on;
  374. };
  375. pp1000_l3a_sdr845: ldo3 {
  376. regulator-min-microvolt = <1000000>;
  377. regulator-max-microvolt = <1000000>;
  378. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  379. };
  380. vdd_wcss_cx:
  381. vdd_wcss_mx:
  382. vdda_wcss_pll:
  383. src_pp800_l5a: ldo5 {
  384. regulator-min-microvolt = <800000>;
  385. regulator-max-microvolt = <800000>;
  386. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  387. };
  388. vddpx_13:
  389. src_pp1800_l6a: ldo6 {
  390. regulator-min-microvolt = <1856000>;
  391. regulator-max-microvolt = <1856000>;
  392. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  393. };
  394. pp1800_l7a_wcn3990: ldo7 {
  395. regulator-min-microvolt = <1800000>;
  396. regulator-max-microvolt = <1800000>;
  397. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  398. };
  399. src_pp1200_l8a: ldo8 {
  400. regulator-min-microvolt = <1200000>;
  401. regulator-max-microvolt = <1248000>;
  402. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  403. };
  404. pp1800_dx_pen:
  405. src_pp1800_l9a: ldo9 {
  406. regulator-min-microvolt = <1800000>;
  407. regulator-max-microvolt = <1800000>;
  408. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  409. };
  410. src_pp1800_l10a: ldo10 {
  411. regulator-min-microvolt = <1800000>;
  412. regulator-max-microvolt = <1800000>;
  413. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  414. };
  415. pp1000_l11a_sdr845: ldo11 {
  416. regulator-min-microvolt = <1000000>;
  417. regulator-max-microvolt = <1048000>;
  418. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  419. };
  420. vdd_qfprom:
  421. vdd_qfprom_sp:
  422. vdda_apc1_cs_1p8:
  423. vdda_gfx_cs_1p8:
  424. vdda_qrefs_1p8:
  425. vdda_qusb_hs0_1p8:
  426. vddpx_11:
  427. src_pp1800_l12a: ldo12 {
  428. regulator-min-microvolt = <1800000>;
  429. regulator-max-microvolt = <1800000>;
  430. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  431. };
  432. vddpx_2:
  433. src_pp2950_l13a: ldo13 {
  434. regulator-min-microvolt = <1800000>;
  435. regulator-max-microvolt = <2960000>;
  436. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  437. };
  438. src_pp1800_l14a: ldo14 {
  439. regulator-min-microvolt = <1800000>;
  440. regulator-max-microvolt = <1800000>;
  441. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  442. };
  443. src_pp1800_l15a: ldo15 {
  444. regulator-min-microvolt = <1800000>;
  445. regulator-max-microvolt = <1800000>;
  446. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  447. };
  448. pp2700_l16a: ldo16 {
  449. regulator-min-microvolt = <2704000>;
  450. regulator-max-microvolt = <2704000>;
  451. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  452. };
  453. src_pp1300_l17a: ldo17 {
  454. regulator-min-microvolt = <1304000>;
  455. regulator-max-microvolt = <1304000>;
  456. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  457. };
  458. pp2700_l18a: ldo18 {
  459. regulator-min-microvolt = <2704000>;
  460. regulator-max-microvolt = <2960000>;
  461. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  462. };
  463. /*
  464. * NOTE: this rail should have been called
  465. * src_pp3300_l19a in the schematic
  466. */
  467. src_pp3000_l19a: ldo19 {
  468. regulator-min-microvolt = <3304000>;
  469. regulator-max-microvolt = <3304000>;
  470. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  471. };
  472. src_pp2950_l20a: ldo20 {
  473. regulator-min-microvolt = <2704000>;
  474. regulator-max-microvolt = <2960000>;
  475. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  476. };
  477. src_pp2950_l21a: ldo21 {
  478. regulator-min-microvolt = <2704000>;
  479. regulator-max-microvolt = <2960000>;
  480. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  481. };
  482. pp3300_hub:
  483. src_pp3300_l22a: ldo22 {
  484. regulator-min-microvolt = <3304000>;
  485. regulator-max-microvolt = <3304000>;
  486. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  487. /*
  488. * HACK: Should add a usb hub node and driver
  489. * to turn this on and off at suspend/resume time
  490. */
  491. regulator-boot-on;
  492. regulator-always-on;
  493. };
  494. pp3300_l23a_ch1_wcn3990: ldo23 {
  495. regulator-min-microvolt = <3000000>;
  496. regulator-max-microvolt = <3312000>;
  497. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  498. };
  499. vdda_qusb_hs0_3p1:
  500. src_pp3075_l24a: ldo24 {
  501. regulator-min-microvolt = <3088000>;
  502. regulator-max-microvolt = <3088000>;
  503. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  504. };
  505. pp3300_l25a_ch0_wcn3990: ldo25 {
  506. regulator-min-microvolt = <3304000>;
  507. regulator-max-microvolt = <3304000>;
  508. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  509. };
  510. pp1200_hub:
  511. vdda_hp_pcie_1p2:
  512. vdda_hv_ebi0:
  513. vdda_hv_ebi1:
  514. vdda_hv_ebi2:
  515. vdda_hv_ebi3:
  516. vdda_mipi_csi_1p25:
  517. vdda_mipi_dsi0_1p2:
  518. vdda_mipi_dsi1_1p2:
  519. vdda_pcie_1p2:
  520. vdda_ufs1_1p2:
  521. vdda_ufs2_1p2:
  522. vdda_usb1_ss_1p2:
  523. vdda_usb2_ss_1p2:
  524. src_pp1200_l26a: ldo26 {
  525. regulator-min-microvolt = <1200000>;
  526. regulator-max-microvolt = <1200000>;
  527. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  528. };
  529. pp3300_dx_pen:
  530. src_pp3300_l28a: ldo28 {
  531. regulator-min-microvolt = <3304000>;
  532. regulator-max-microvolt = <3304000>;
  533. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  534. };
  535. src_pp1800_lvs1: lvs1 {
  536. regulator-min-microvolt = <1800000>;
  537. regulator-max-microvolt = <1800000>;
  538. };
  539. src_pp1800_lvs2: lvs2 {
  540. regulator-min-microvolt = <1800000>;
  541. regulator-max-microvolt = <1800000>;
  542. };
  543. };
  544. pm8005-rpmh-regulators {
  545. compatible = "qcom,pm8005-rpmh-regulators";
  546. qcom,pmic-id = "c";
  547. vdd-s1-supply = <&src_vph_pwr>;
  548. vdd-s2-supply = <&src_vph_pwr>;
  549. vdd-s3-supply = <&src_vph_pwr>;
  550. vdd-s4-supply = <&src_vph_pwr>;
  551. src_pp600_s3c: smps3 {
  552. regulator-min-microvolt = <600000>;
  553. regulator-max-microvolt = <600000>;
  554. };
  555. };
  556. };
  557. &dsi0 {
  558. status = "okay";
  559. vdda-supply = <&vdda_mipi_dsi0_1p2>;
  560. ports {
  561. port@1 {
  562. endpoint {
  563. remote-endpoint = <&sn65dsi86_in>;
  564. data-lanes = <0 1 2 3>;
  565. };
  566. };
  567. };
  568. };
  569. &dsi0_phy {
  570. status = "okay";
  571. vdds-supply = <&vdda_mipi_dsi0_pll>;
  572. };
  573. edp_brij_i2c: &i2c3 {
  574. status = "okay";
  575. clock-frequency = <400000>;
  576. sn65dsi86_bridge: bridge@2d {
  577. compatible = "ti,sn65dsi86";
  578. reg = <0x2d>;
  579. pinctrl-names = "default";
  580. pinctrl-0 = <&edp_brij_en &edp_brij_irq>;
  581. interrupt-parent = <&tlmm>;
  582. interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
  583. enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
  584. vpll-supply = <&src_pp1800_s4a>;
  585. vccio-supply = <&src_pp1800_s4a>;
  586. vcca-supply = <&src_pp1200_l2a>;
  587. vcc-supply = <&src_pp1200_l2a>;
  588. clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
  589. clock-names = "refclk";
  590. no-hpd;
  591. ports {
  592. #address-cells = <1>;
  593. #size-cells = <0>;
  594. port@0 {
  595. reg = <0>;
  596. sn65dsi86_in: endpoint {
  597. remote-endpoint = <&dsi0_out>;
  598. };
  599. };
  600. port@1 {
  601. reg = <1>;
  602. sn65dsi86_out: endpoint {
  603. remote-endpoint = <&panel_in_edp>;
  604. };
  605. };
  606. };
  607. };
  608. };
  609. ap_pen_1v8: &i2c11 {
  610. status = "okay";
  611. clock-frequency = <400000>;
  612. digitizer@9 {
  613. compatible = "wacom,w9013", "hid-over-i2c";
  614. reg = <0x9>;
  615. pinctrl-names = "default";
  616. pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>;
  617. vdd-supply = <&pp3300_dx_pen>;
  618. vddl-supply = <&pp1800_dx_pen>;
  619. post-power-on-delay-ms = <100>;
  620. interrupt-parent = <&tlmm>;
  621. interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
  622. hid-descr-addr = <0x1>;
  623. };
  624. };
  625. amp_i2c: &i2c12 {
  626. status = "okay";
  627. clock-frequency = <400000>;
  628. };
  629. ap_ts_i2c: &i2c14 {
  630. status = "okay";
  631. clock-frequency = <400000>;
  632. touchscreen@10 {
  633. compatible = "elan,ekth3500";
  634. reg = <0x10>;
  635. pinctrl-names = "default";
  636. pinctrl-0 = <&ts_int_l &ts_reset_l>;
  637. interrupt-parent = <&tlmm>;
  638. interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
  639. vcc33-supply = <&src_pp3300_l28a>;
  640. reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
  641. };
  642. };
  643. &gmu {
  644. status = "okay";
  645. };
  646. &gpu {
  647. status = "okay";
  648. };
  649. &ipa {
  650. status = "okay";
  651. modem-init;
  652. };
  653. &lpasscc {
  654. status = "okay";
  655. };
  656. &mdss {
  657. status = "okay";
  658. };
  659. /*
  660. * Cheza fw does not properly program the GPU aperture to allow the
  661. * GPU to update the SMMU pagetables for context switches. Work
  662. * around this by dropping the "qcom,adreno-smmu" compat string.
  663. */
  664. &adreno_smmu {
  665. compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
  666. };
  667. &mss_pil {
  668. status = "okay";
  669. iommus = <&apps_smmu 0x781 0x0>,
  670. <&apps_smmu 0x724 0x3>;
  671. };
  672. &pm8998_pwrkey {
  673. status = "disabled";
  674. };
  675. &qupv3_id_0 {
  676. status = "okay";
  677. iommus = <&apps_smmu 0x0 0x3>;
  678. };
  679. &qupv3_id_1 {
  680. status = "okay";
  681. iommus = <&apps_smmu 0x6c0 0x3>;
  682. };
  683. &sdhc_2 {
  684. status = "okay";
  685. pinctrl-names = "default";
  686. pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>;
  687. vmmc-supply = <&src_pp2950_l21a>;
  688. vqmmc-supply = <&vddpx_2>;
  689. cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
  690. };
  691. &spi0 {
  692. status = "okay";
  693. };
  694. &spi5 {
  695. status = "okay";
  696. tpm@0 {
  697. compatible = "google,cr50";
  698. reg = <0>;
  699. pinctrl-names = "default";
  700. pinctrl-0 = <&h1_ap_int_odl>;
  701. spi-max-frequency = <800000>;
  702. interrupt-parent = <&tlmm>;
  703. interrupts = <129 IRQ_TYPE_EDGE_RISING>;
  704. };
  705. };
  706. &spi10 {
  707. status = "okay";
  708. cros_ec: ec@0 {
  709. compatible = "google,cros-ec-spi";
  710. reg = <0>;
  711. interrupt-parent = <&tlmm>;
  712. interrupts = <122 IRQ_TYPE_LEVEL_LOW>;
  713. pinctrl-names = "default";
  714. pinctrl-0 = <&ec_ap_int_l>;
  715. spi-max-frequency = <3000000>;
  716. cros_ec_pwm: pwm {
  717. compatible = "google,cros-ec-pwm";
  718. #pwm-cells = <1>;
  719. };
  720. i2c_tunnel: i2c-tunnel {
  721. compatible = "google,cros-ec-i2c-tunnel";
  722. google,remote-bus = <0>;
  723. #address-cells = <1>;
  724. #size-cells = <0>;
  725. };
  726. };
  727. };
  728. #include <arm/cros-ec-keyboard.dtsi>
  729. #include <arm/cros-ec-sbs.dtsi>
  730. &uart6 {
  731. status = "okay";
  732. bluetooth: wcn3990-bt {
  733. compatible = "qcom,wcn3990-bt";
  734. vddio-supply = <&src_pp1800_s4a>;
  735. vddxo-supply = <&pp1800_l7a_wcn3990>;
  736. vddrf-supply = <&src_pp1300_l17a>;
  737. vddch0-supply = <&pp3300_l25a_ch0_wcn3990>;
  738. max-speed = <3200000>;
  739. };
  740. };
  741. &uart9 {
  742. status = "okay";
  743. };
  744. &ufs_mem_hc {
  745. status = "okay";
  746. reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
  747. vcc-supply = <&src_pp2950_l20a>;
  748. vcc-max-microamp = <600000>;
  749. };
  750. &ufs_mem_phy {
  751. status = "okay";
  752. vdda-phy-supply = <&vdda_ufs1_core>;
  753. vdda-pll-supply = <&vdda_ufs1_1p2>;
  754. };
  755. &usb_1 {
  756. status = "okay";
  757. /* We'll use this as USB 2.0 only */
  758. qcom,select-utmi-as-pipe-clk;
  759. };
  760. &usb_1_dwc3 {
  761. /*
  762. * The hardware design intends this port to be hooked up in peripheral
  763. * mode, so we'll hardcode it here. Some details:
  764. * - SDM845 expects only a single Type C connector so it has only one
  765. * native Type C port but cheza has two Type C connectors.
  766. * - The only source of DP is the single native Type C port.
  767. * - On cheza we want to be able to hook DP up to _either_ of the
  768. * two Type C connectors and want to be able to achieve 4 lanes of DP.
  769. * - When you configure a Type C port for 4 lanes of DP you lose USB3.
  770. * - In order to make everything work, the native Type C port is always
  771. * configured as 4-lanes DP so it's always available.
  772. * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then
  773. * sent to the two Type C connectors.
  774. * - The extra USB2 lines from the native Type C port are always
  775. * setup as "peripheral" so that we can mux them over to one connector
  776. * or the other if someone needs the connector configured as a gadget
  777. * (but they only get USB2 speeds).
  778. *
  779. * All the hardware muxes would allow us to hook things up in different
  780. * ways to some potential benefit for static configurations (you could
  781. * achieve extra USB2 bandwidth by using two different ports for the
  782. * two connectors or possibly even get USB3 peripheral mode), but in
  783. * each case you end up forcing to disconnect/reconnect an in-use
  784. * USB session in some cases depending on what you hotplug into the
  785. * other connector. Thus hardcoding this as peripheral makes sense.
  786. */
  787. dr_mode = "peripheral";
  788. /*
  789. * We always need the high speed pins as 4-lanes DP in case someone
  790. * hotplugs a DP peripheral. Thus limit this port to a max of high
  791. * speed.
  792. */
  793. maximum-speed = "high-speed";
  794. /*
  795. * We don't need the usb3-phy since we run in highspeed mode always, so
  796. * re-define these properties removing the superspeed USB PHY reference.
  797. */
  798. phys = <&usb_1_hsphy>;
  799. phy-names = "usb2-phy";
  800. };
  801. &usb_1_hsphy {
  802. status = "okay";
  803. vdd-supply = <&vdda_usb1_ss_core>;
  804. vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
  805. vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
  806. qcom,imp-res-offset-value = <8>;
  807. qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
  808. qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
  809. qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
  810. };
  811. &usb_2 {
  812. status = "okay";
  813. };
  814. &usb_2_dwc3 {
  815. /* We have this hooked up to a hub and we always use in host mode */
  816. dr_mode = "host";
  817. };
  818. &usb_2_hsphy {
  819. status = "okay";
  820. vdd-supply = <&vdda_usb2_ss_core>;
  821. vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
  822. vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
  823. qcom,imp-res-offset-value = <8>;
  824. qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
  825. };
  826. &usb_2_qmpphy {
  827. status = "okay";
  828. vdda-phy-supply = <&vdda_usb2_ss_1p2>;
  829. vdda-pll-supply = <&vdda_usb2_ss_core>;
  830. };
  831. &wifi {
  832. status = "okay";
  833. vdd-0.8-cx-mx-supply = <&src_pp800_l5a >;
  834. vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>;
  835. vdd-1.3-rfa-supply = <&src_pp1300_l17a>;
  836. vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>;
  837. };
  838. /* PINCTRL - additions to nodes defined in sdm845.dtsi */
  839. &qspi_cs0 {
  840. pinconf {
  841. pins = "gpio90";
  842. bias-disable;
  843. };
  844. };
  845. &qspi_clk {
  846. pinconf {
  847. pins = "gpio95";
  848. bias-disable;
  849. };
  850. };
  851. &qspi_data01 {
  852. pinconf {
  853. pins = "gpio91", "gpio92";
  854. /* High-Z when no transfers; nice to park the lines */
  855. bias-pull-up;
  856. };
  857. };
  858. &qup_i2c3_default {
  859. pinconf {
  860. pins = "gpio41", "gpio42";
  861. drive-strength = <2>;
  862. /* Has external pullup */
  863. bias-disable;
  864. };
  865. };
  866. &qup_i2c11_default {
  867. pinconf {
  868. pins = "gpio31", "gpio32";
  869. drive-strength = <2>;
  870. /* Has external pullup */
  871. bias-disable;
  872. };
  873. };
  874. &qup_i2c12_default {
  875. pinconf {
  876. pins = "gpio49", "gpio50";
  877. drive-strength = <2>;
  878. /* Has external pullup */
  879. bias-disable;
  880. };
  881. };
  882. &qup_i2c14_default {
  883. pinconf {
  884. pins = "gpio33", "gpio34";
  885. drive-strength = <2>;
  886. /* Has external pullup */
  887. bias-disable;
  888. };
  889. };
  890. &qup_spi0_default {
  891. pinconf {
  892. pins = "gpio0", "gpio1", "gpio2", "gpio3";
  893. drive-strength = <2>;
  894. bias-disable;
  895. };
  896. };
  897. &qup_spi5_default {
  898. pinconf {
  899. pins = "gpio85", "gpio86", "gpio87", "gpio88";
  900. drive-strength = <2>;
  901. bias-disable;
  902. };
  903. };
  904. &qup_spi10_default {
  905. pinconf {
  906. pins = "gpio53", "gpio54", "gpio55", "gpio56";
  907. drive-strength = <2>;
  908. bias-disable;
  909. };
  910. };
  911. &qup_uart6_default {
  912. /* Change pinmux to all 4 pins since CTS and RTS are connected */
  913. pinmux {
  914. pins = "gpio45", "gpio46",
  915. "gpio47", "gpio48";
  916. };
  917. pinconf-cts {
  918. /*
  919. * Configure a pull-down on 45 (CTS) to match the pull of
  920. * the Bluetooth module.
  921. */
  922. pins = "gpio45";
  923. bias-pull-down;
  924. };
  925. pinconf-rts-tx {
  926. /* We'll drive 46 (RTS) and 47 (TX), so no pull */
  927. pins = "gpio46", "gpio47";
  928. drive-strength = <2>;
  929. bias-disable;
  930. };
  931. pinconf-rx {
  932. /*
  933. * Configure a pull-up on 48 (RX). This is needed to avoid
  934. * garbage data when the TX pin of the Bluetooth module is
  935. * in tri-state (module powered off or not driving the
  936. * signal yet).
  937. */
  938. pins = "gpio48";
  939. bias-pull-up;
  940. };
  941. };
  942. &qup_uart9_default {
  943. pinconf-tx {
  944. pins = "gpio4";
  945. drive-strength = <2>;
  946. bias-disable;
  947. };
  948. pinconf-rx {
  949. pins = "gpio5";
  950. drive-strength = <2>;
  951. bias-pull-up;
  952. };
  953. };
  954. /* PINCTRL - board-specific pinctrl */
  955. &pm8005_gpio {
  956. gpio-line-names = "",
  957. "",
  958. "SLB",
  959. "";
  960. };
  961. &pm8998_adc {
  962. adc-chan@4d {
  963. reg = <ADC5_AMUX_THM1_100K_PU>;
  964. label = "sdm_temp";
  965. };
  966. adc-chan@4e {
  967. reg = <ADC5_AMUX_THM2_100K_PU>;
  968. label = "quiet_temp";
  969. };
  970. adc-chan@4f {
  971. reg = <ADC5_AMUX_THM3_100K_PU>;
  972. label = "lte_temp_1";
  973. };
  974. adc-chan@50 {
  975. reg = <ADC5_AMUX_THM4_100K_PU>;
  976. label = "lte_temp_2";
  977. };
  978. adc-chan@51 {
  979. reg = <ADC5_AMUX_THM5_100K_PU>;
  980. label = "charger_temp";
  981. };
  982. };
  983. &pm8998_gpio {
  984. gpio-line-names = "",
  985. "",
  986. "SW_CTRL",
  987. "",
  988. "",
  989. "",
  990. "",
  991. "",
  992. "",
  993. "",
  994. "",
  995. "",
  996. "",
  997. "",
  998. "",
  999. "",
  1000. "",
  1001. "",
  1002. "",
  1003. "",
  1004. "",
  1005. "CFG_OPT1",
  1006. "WCSS_PWR_REQ",
  1007. "",
  1008. "CFG_OPT2",
  1009. "SLB";
  1010. };
  1011. &tlmm {
  1012. /*
  1013. * pinctrl settings for pins that have no real owners.
  1014. */
  1015. pinctrl-names = "default", "sleep";
  1016. pinctrl-0 = <&bios_flash_wp_r_l>,
  1017. <&ap_suspend_l_deassert>;
  1018. pinctrl-1 = <&bios_flash_wp_r_l>,
  1019. <&ap_suspend_l_assert>;
  1020. /*
  1021. * Hogs prevent usermode from changing the value. A GPIO can be both
  1022. * here and in the pinctrl section.
  1023. */
  1024. ap-suspend-l-hog {
  1025. gpio-hog;
  1026. gpios = <126 GPIO_ACTIVE_LOW>;
  1027. output-low;
  1028. };
  1029. ap_edp_bklten: ap-edp-bklten {
  1030. pinmux {
  1031. pins = "gpio37";
  1032. function = "gpio";
  1033. };
  1034. pinconf {
  1035. pins = "gpio37";
  1036. drive-strength = <2>;
  1037. bias-disable;
  1038. };
  1039. };
  1040. bios_flash_wp_r_l: bios-flash-wp-r-l {
  1041. pinmux {
  1042. pins = "gpio128";
  1043. function = "gpio";
  1044. input-enable;
  1045. };
  1046. pinconf {
  1047. pins = "gpio128";
  1048. bias-disable;
  1049. };
  1050. };
  1051. ec_ap_int_l: ec-ap-int-l {
  1052. pinmux {
  1053. pins = "gpio122";
  1054. function = "gpio";
  1055. input-enable;
  1056. };
  1057. pinconf {
  1058. pins = "gpio122";
  1059. bias-pull-up;
  1060. };
  1061. };
  1062. edp_brij_en: edp-brij-en {
  1063. pinmux {
  1064. pins = "gpio102";
  1065. function = "gpio";
  1066. };
  1067. pinconf {
  1068. pins = "gpio102";
  1069. drive-strength = <2>;
  1070. bias-disable;
  1071. };
  1072. };
  1073. edp_brij_irq: edp-brij-irq {
  1074. pinmux {
  1075. pins = "gpio10";
  1076. function = "gpio";
  1077. };
  1078. pinconf {
  1079. pins = "gpio10";
  1080. drive-strength = <2>;
  1081. bias-pull-down;
  1082. };
  1083. };
  1084. en_pp3300_dx_edp: en-pp3300-dx-edp {
  1085. pinmux {
  1086. pins = "gpio43";
  1087. function = "gpio";
  1088. };
  1089. pinconf {
  1090. pins = "gpio43";
  1091. drive-strength = <2>;
  1092. bias-disable;
  1093. };
  1094. };
  1095. h1_ap_int_odl: h1-ap-int-odl {
  1096. pinmux {
  1097. pins = "gpio129";
  1098. function = "gpio";
  1099. input-enable;
  1100. };
  1101. pinconf {
  1102. pins = "gpio129";
  1103. bias-pull-up;
  1104. };
  1105. };
  1106. pen_eject_odl: pen-eject-odl {
  1107. pinmux {
  1108. pins = "gpio119";
  1109. function = "gpio";
  1110. bias-pull-up;
  1111. };
  1112. };
  1113. pen_irq_l: pen-irq-l {
  1114. pinmux {
  1115. pins = "gpio24";
  1116. function = "gpio";
  1117. };
  1118. pinconf {
  1119. pins = "gpio24";
  1120. /* Has external pullup */
  1121. bias-disable;
  1122. };
  1123. };
  1124. pen_pdct_l: pen-pdct-l {
  1125. pinmux {
  1126. pins = "gpio63";
  1127. function = "gpio";
  1128. };
  1129. pinconf {
  1130. pins = "gpio63";
  1131. /* Has external pullup */
  1132. bias-disable;
  1133. };
  1134. };
  1135. pen_rst_l: pen-rst-l {
  1136. pinmux {
  1137. pins = "gpio23";
  1138. function = "gpio";
  1139. };
  1140. pinconf {
  1141. pins = "gpio23";
  1142. bias-disable;
  1143. drive-strength = <2>;
  1144. /*
  1145. * The pen driver doesn't currently support
  1146. * driving this reset line. By specifying
  1147. * output-high here we're relying on the fact
  1148. * that this pin has a default pulldown at boot
  1149. * (which makes sure the pen was in reset if it
  1150. * was powered) and then we set it high here to
  1151. * take it out of reset. Better would be if the
  1152. * pen driver could control this and we could
  1153. * remove "output-high" here.
  1154. */
  1155. output-high;
  1156. };
  1157. };
  1158. sdc2_clk: sdc2-clk {
  1159. pinconf {
  1160. pins = "sdc2_clk";
  1161. bias-disable;
  1162. /*
  1163. * It seems that mmc_test reports errors if drive
  1164. * strength is not 16.
  1165. */
  1166. drive-strength = <16>;
  1167. };
  1168. };
  1169. sdc2_cmd: sdc2-cmd {
  1170. pinconf {
  1171. pins = "sdc2_cmd";
  1172. bias-pull-up;
  1173. drive-strength = <16>;
  1174. };
  1175. };
  1176. sdc2_data: sdc2-data {
  1177. pinconf {
  1178. pins = "sdc2_data";
  1179. bias-pull-up;
  1180. drive-strength = <16>;
  1181. };
  1182. };
  1183. sd_cd_odl: sd-cd-odl {
  1184. pinmux {
  1185. pins = "gpio44";
  1186. function = "gpio";
  1187. };
  1188. pinconf {
  1189. pins = "gpio44";
  1190. bias-pull-up;
  1191. };
  1192. };
  1193. ts_int_l: ts-int-l {
  1194. pinmux {
  1195. pins = "gpio125";
  1196. function = "gpio";
  1197. };
  1198. pinconf {
  1199. pins = "gpio125";
  1200. bias-pull-up;
  1201. };
  1202. };
  1203. ts_reset_l: ts-reset-l {
  1204. pinmux {
  1205. pins = "gpio118";
  1206. function = "gpio";
  1207. };
  1208. pinconf {
  1209. pins = "gpio118";
  1210. bias-disable;
  1211. drive-strength = <2>;
  1212. };
  1213. };
  1214. ap_suspend_l_assert: ap_suspend_l_assert {
  1215. config {
  1216. pins = "gpio126";
  1217. function = "gpio";
  1218. bias-disable;
  1219. drive-strength = <2>;
  1220. output-low;
  1221. };
  1222. };
  1223. ap_suspend_l_deassert: ap_suspend_l_deassert {
  1224. config {
  1225. pins = "gpio126";
  1226. function = "gpio";
  1227. bias-disable;
  1228. drive-strength = <2>;
  1229. output-high;
  1230. };
  1231. };
  1232. };
  1233. &venus {
  1234. status = "okay";
  1235. video-firmware {
  1236. iommus = <&apps_smmu 0x10b2 0x0>;
  1237. };
  1238. };