sdm845-cheza-r3.dts 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174
  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Google Cheza board device tree source
  4. *
  5. * Copyright 2018 Google LLC.
  6. */
  7. /dts-v1/;
  8. #include "sdm845-cheza.dtsi"
  9. / {
  10. model = "Google Cheza (rev3+)";
  11. compatible = "google,cheza", "qcom,sdm845";
  12. };
  13. /* PINCTRL - board-specific pinctrl */
  14. &tlmm {
  15. gpio-line-names = "AP_SPI_FP_MISO",
  16. "AP_SPI_FP_MOSI",
  17. "AP_SPI_FP_CLK",
  18. "AP_SPI_FP_CS_L",
  19. "UART_AP_TX_DBG_RX",
  20. "UART_DBG_TX_AP_RX",
  21. "BRIJ_SUSPEND",
  22. "FP_RST_L",
  23. "FCAM_EN",
  24. "",
  25. "EDP_BRIJ_IRQ",
  26. "EC_IN_RW_ODL",
  27. "",
  28. "RCAM_MCLK",
  29. "FCAM_MCLK",
  30. "",
  31. "RCAM_EN",
  32. "CCI0_SDA",
  33. "CCI0_SCL",
  34. "CCI1_SDA",
  35. "CCI1_SCL",
  36. "FCAM_RST_L",
  37. "FPMCU_BOOT0",
  38. "PEN_RST_L",
  39. "PEN_IRQ_L",
  40. "FPMCU_SEL_OD",
  41. "RCAM_VSYNC",
  42. "ESIM_MISO",
  43. "ESIM_MOSI",
  44. "ESIM_CLK",
  45. "ESIM_CS_L",
  46. "AP_PEN_1V8_SDA",
  47. "AP_PEN_1V8_SCL",
  48. "AP_TS_I2C_SDA",
  49. "AP_TS_I2C_SCL",
  50. "RCAM_RST_L",
  51. "",
  52. "AP_EDP_BKLTEN",
  53. "AP_BRD_ID0",
  54. "BOOT_CONFIG_4",
  55. "AMP_IRQ_L",
  56. "EDP_BRIJ_I2C_SDA",
  57. "EDP_BRIJ_I2C_SCL",
  58. "EN_PP3300_DX_EDP",
  59. "SD_CD_ODL",
  60. "BT_UART_RTS",
  61. "BT_UART_CTS",
  62. "BT_UART_RXD",
  63. "BT_UART_TXD",
  64. "AMP_I2C_SDA",
  65. "AMP_I2C_SCL",
  66. "AP_BRD_ID2",
  67. "",
  68. "AP_EC_SPI_CLK",
  69. "AP_EC_SPI_CS_L",
  70. "AP_EC_SPI_MISO",
  71. "AP_EC_SPI_MOSI",
  72. "FORCED_USB_BOOT",
  73. "AMP_BCLK",
  74. "AMP_LRCLK",
  75. "AMP_DOUT",
  76. "AMP_DIN",
  77. "AP_BRD_ID1",
  78. "PEN_PDCT_L",
  79. "HP_MCLK",
  80. "HP_BCLK",
  81. "HP_LRCLK",
  82. "HP_DOUT",
  83. "HP_DIN",
  84. "",
  85. "",
  86. "",
  87. "",
  88. "BT_SLIMBUS_DATA",
  89. "BT_SLIMBUS_CLK",
  90. "AMP_RESET_L",
  91. "",
  92. "FCAM_VSYNC",
  93. "",
  94. "AP_SKU_ID0",
  95. "EC_WOV_BCLK",
  96. "EC_WOV_LRCLK",
  97. "EC_WOV_DOUT",
  98. "",
  99. "",
  100. "AP_H1_SPI_MISO",
  101. "AP_H1_SPI_MOSI",
  102. "AP_H1_SPI_CLK",
  103. "AP_H1_SPI_CS_L",
  104. "",
  105. "AP_SPI_CS0_L",
  106. "AP_SPI_MOSI",
  107. "AP_SPI_MISO",
  108. "",
  109. "",
  110. "AP_SPI_CLK",
  111. "",
  112. "RFFE6_CLK",
  113. "RFFE6_DATA",
  114. "BOOT_CONFIG_1",
  115. "BOOT_CONFIG_2",
  116. "BOOT_CONFIG_0",
  117. "EDP_BRIJ_EN",
  118. "",
  119. "USB_HS_TX_EN",
  120. "UIM2_DATA",
  121. "UIM2_CLK",
  122. "UIM2_RST",
  123. "UIM2_PRESENT",
  124. "UIM1_DATA",
  125. "UIM1_CLK",
  126. "UIM1_RST",
  127. "",
  128. "AP_SKU_ID1",
  129. "SDM_GRFC_8",
  130. "SDM_GRFC_9",
  131. "AP_RST_REQ",
  132. "HP_IRQ",
  133. "TS_RESET_L",
  134. "PEN_EJECT_ODL",
  135. "HUB_RST_L",
  136. "FP_TO_AP_IRQ",
  137. "AP_EC_INT_L",
  138. "",
  139. "",
  140. "TS_INT_L",
  141. "AP_SUSPEND_L",
  142. "SDM_GRFC_3",
  143. /*
  144. * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics
  145. * call it BIOS_FLASH_WP_R_L.
  146. */
  147. "AP_FLASH_WP_L",
  148. "H1_AP_INT_ODL",
  149. "QLINK_REQ",
  150. "QLINK_EN",
  151. "SDM_GRFC_2",
  152. "BOOT_CONFIG_3",
  153. "WMSS_RESET_L",
  154. "SDM_GRFC_0",
  155. "SDM_GRFC_1",
  156. "RFFE3_DATA",
  157. "RFFE3_CLK",
  158. "RFFE4_DATA",
  159. "RFFE4_CLK",
  160. "RFFE5_DATA",
  161. "RFFE5_CLK",
  162. "GNSS_EN",
  163. "WCI2_LTE_COEX_RXD",
  164. "WCI2_LTE_COEX_TXD",
  165. "AP_RAM_ID0",
  166. "AP_RAM_ID1",
  167. "RFFE1_DATA",
  168. "RFFE1_CLK";
  169. };