sc7280-qcard.dtsi 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684
  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * sc7280 Qcard device tree source
  4. *
  5. * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if
  6. * stuffed) on it. This device tree tries to encapsulate all the things that
  7. * all boards using Qcard will have in common. Given that there are stuffing
  8. * options, some things may be left with status "disabled" and enabled in
  9. * the actual board device tree files.
  10. *
  11. * Copyright 2022 Google LLC.
  12. */
  13. #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
  14. #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
  15. #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
  16. #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
  17. #include "sc7280.dtsi"
  18. /* PMICs depend on spmi_bus label and so must come after SoC */
  19. #include "pm7325.dtsi"
  20. #include "pm8350c.dtsi"
  21. #include "pmk8350.dtsi"
  22. / {
  23. aliases {
  24. bluetooth0 = &bluetooth;
  25. serial0 = &uart5;
  26. serial1 = &uart7;
  27. wifi0 = &wifi;
  28. };
  29. wcd9385: audio-codec-1 {
  30. compatible = "qcom,wcd9385-codec";
  31. pinctrl-names = "default", "sleep";
  32. pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
  33. pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>;
  34. reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
  35. us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
  36. qcom,rx-device = <&wcd_rx>;
  37. qcom,tx-device = <&wcd_tx>;
  38. vdd-rxtx-supply = <&vreg_l18b_1p8>;
  39. vdd-io-supply = <&vreg_l18b_1p8>;
  40. vdd-buck-supply = <&vreg_l17b_1p8>;
  41. vdd-mic-bias-supply = <&vreg_bob>;
  42. qcom,micbias1-microvolt = <1800000>;
  43. qcom,micbias2-microvolt = <1800000>;
  44. qcom,micbias3-microvolt = <1800000>;
  45. qcom,micbias4-microvolt = <1800000>;
  46. qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
  47. 500000 500000 500000>;
  48. qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
  49. qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
  50. #sound-dai-cells = <1>;
  51. status = "disabled";
  52. };
  53. pm8350c_pwm_backlight: backlight {
  54. compatible = "pwm-backlight";
  55. status = "disabled";
  56. enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>;
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&pmic_edp_bl_en>;
  59. pwms = <&pm8350c_pwm 3 65535>;
  60. };
  61. };
  62. &apps_rsc {
  63. /*
  64. * Regulators are given labels corresponding to the various names
  65. * they are referred to on schematics. They are also given labels
  66. * corresponding to named voltage inputs on the SoC or components
  67. * bundled with the SoC (like radio companion chips). We totally
  68. * ignore it when one regulator is the input to another regulator.
  69. * That's handled automatically by the initial config given to
  70. * RPMH by the firmware.
  71. *
  72. * Regulators that the HLOS (High Level OS) doesn't touch at all
  73. * are left out of here since they are managed elsewhere.
  74. */
  75. pm7325-regulators {
  76. compatible = "qcom,pm7325-rpmh-regulators";
  77. qcom,pmic-id = "b";
  78. vdd19_pmu_pcie_i:
  79. vdd19_pmu_rfa_i:
  80. vreg_s1b_1p856: smps1 {
  81. regulator-min-microvolt = <1856000>;
  82. regulator-max-microvolt = <2040000>;
  83. };
  84. vdd_pmu_aon_i:
  85. vdd09_pmu_rfa_i:
  86. vdd095_mx_pmu:
  87. vdd095_pmu:
  88. vreg_s7b_0p952: smps7 {
  89. regulator-min-microvolt = <535000>;
  90. regulator-max-microvolt = <1120000>;
  91. };
  92. vdd13_pmu_rfa_i:
  93. vdd13_pmu_pcie_i:
  94. vreg_s8b_1p256: smps8 {
  95. regulator-min-microvolt = <1256000>;
  96. regulator-max-microvolt = <1500000>;
  97. };
  98. vdd_a_usbssdp_0_core:
  99. vreg_l1b_0p912: ldo1 {
  100. regulator-min-microvolt = <825000>;
  101. regulator-max-microvolt = <925000>;
  102. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  103. };
  104. vdd_a_usbhs_3p1:
  105. vreg_l2b_3p072: ldo2 {
  106. regulator-min-microvolt = <2700000>;
  107. regulator-max-microvolt = <3544000>;
  108. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  109. };
  110. vdd_a_csi_0_1_1p2:
  111. vdd_a_csi_2_3_1p2:
  112. vdd_a_csi_4_1p2:
  113. vdd_a_dsi_0_1p2:
  114. vdd_a_edp_0_1p2:
  115. vdd_a_qlink_0_1p2:
  116. vdd_a_qlink_1_1p2:
  117. vdd_a_pcie_0_1p2:
  118. vdd_a_pcie_1_1p2:
  119. vdd_a_ufs_0_1p2:
  120. vdd_a_usbssdp_0_1p2:
  121. vreg_l6b_1p2: ldo6 {
  122. regulator-min-microvolt = <1140000>;
  123. regulator-max-microvolt = <1260000>;
  124. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  125. };
  126. /*
  127. * Despite the fact that this is named to be 2.5V on the
  128. * schematic, it powers eMMC which doesn't accept 2.5V
  129. */
  130. vreg_l7b_2p5: ldo7 {
  131. regulator-min-microvolt = <2960000>;
  132. regulator-max-microvolt = <2960000>;
  133. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  134. };
  135. vreg_l17b_1p8: ldo17 {
  136. regulator-min-microvolt = <1700000>;
  137. regulator-max-microvolt = <1900000>;
  138. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  139. };
  140. vdd_px_wcd9385:
  141. vdd_txrx:
  142. vddpx_0:
  143. vddpx_3:
  144. vddpx_7:
  145. vreg_l18b_1p8: ldo18 {
  146. regulator-min-microvolt = <1800000>;
  147. regulator-max-microvolt = <2000000>;
  148. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  149. };
  150. vdd_1p8:
  151. vdd_px_sdr735:
  152. vdd_pxm:
  153. vdd18_io:
  154. vddio_px_1:
  155. vddio_px_2:
  156. vddio_px_3:
  157. vddpx_ts:
  158. vddpx_wl4otp:
  159. vreg_l19b_1p8: ldo19 {
  160. regulator-min-microvolt = <1800000>;
  161. regulator-max-microvolt = <1800000>;
  162. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  163. };
  164. };
  165. pm8350c-regulators {
  166. compatible = "qcom,pm8350c-rpmh-regulators";
  167. qcom,pmic-id = "c";
  168. vdd22_wlbtpa_ch0:
  169. vdd22_wlbtpa_ch1:
  170. vdd22_wlbtppa_ch0:
  171. vdd22_wlbtppa_ch1:
  172. vdd22_wlpa5g_ch0:
  173. vdd22_wlpa5g_ch1:
  174. vdd22_wlppa5g_ch0:
  175. vdd22_wlppa5g_ch1:
  176. vreg_s1c_2p2: smps1 {
  177. regulator-min-microvolt = <2190000>;
  178. regulator-max-microvolt = <2210000>;
  179. };
  180. lp4_vdd2_1p052:
  181. vreg_s9c_0p676: smps9 {
  182. regulator-min-microvolt = <1010000>;
  183. regulator-max-microvolt = <1170000>;
  184. };
  185. vdda_apc_cs_1p8:
  186. vdda_gfx_cs_1p8:
  187. vdda_turing_q6_cs_1p8:
  188. vdd_a_cxo_1p8:
  189. vdd_a_qrefs_1p8:
  190. vdd_a_usbhs_1p8:
  191. vdd_qfprom:
  192. vreg_l1c_1p8: ldo1 {
  193. regulator-min-microvolt = <1800000>;
  194. regulator-max-microvolt = <1980000>;
  195. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  196. };
  197. vreg_l2c_1p8: ldo2 {
  198. regulator-min-microvolt = <1620000>;
  199. regulator-max-microvolt = <1980000>;
  200. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  201. };
  202. vreg_l3c_3p0: ldo3 {
  203. regulator-min-microvolt = <2800000>;
  204. regulator-max-microvolt = <3540000>;
  205. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  206. };
  207. vddpx_5:
  208. vreg_l4c_1p8_3p0: ldo4 {
  209. regulator-min-microvolt = <1620000>;
  210. regulator-max-microvolt = <3300000>;
  211. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  212. };
  213. vddpx_6:
  214. vreg_l5c_1p8_3p0: ldo5 {
  215. regulator-min-microvolt = <1620000>;
  216. regulator-max-microvolt = <3300000>;
  217. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  218. };
  219. vddpx_2:
  220. vreg_l6c_2p96: ldo6 {
  221. regulator-min-microvolt = <1800000>;
  222. regulator-max-microvolt = <2950000>;
  223. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  224. };
  225. vreg_l7c_3p0: ldo7 {
  226. regulator-min-microvolt = <3000000>;
  227. regulator-max-microvolt = <3544000>;
  228. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  229. };
  230. vreg_l8c_1p8: ldo8 {
  231. regulator-min-microvolt = <1620000>;
  232. regulator-max-microvolt = <2000000>;
  233. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  234. };
  235. vreg_l9c_2p96: ldo9 {
  236. regulator-min-microvolt = <2960000>;
  237. regulator-max-microvolt = <2960000>;
  238. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  239. };
  240. vdd_a_csi_0_1_0p9:
  241. vdd_a_csi_2_3_0p9:
  242. vdd_a_csi_4_0p9:
  243. vdd_a_dsi_0_0p9:
  244. vdd_a_dsi_0_pll_0p9:
  245. vdd_a_edp_0_0p9:
  246. vdd_a_gnss_0p9:
  247. vdd_a_pcie_0_core:
  248. vdd_a_pcie_1_core:
  249. vdd_a_qlink_0_0p9:
  250. vdd_a_qlink_0_0p9_ck:
  251. vdd_a_qlink_1_0p9:
  252. vdd_a_qlink_1_0p9_ck:
  253. vdd_a_qrefs_0p875_0:
  254. vdd_a_qrefs_0p875_1:
  255. vdd_a_qrefs_0p875_2:
  256. vdd_a_qrefs_0p875_3:
  257. vdd_a_qrefs_0p875_4_5:
  258. vdd_a_qrefs_0p875_6:
  259. vdd_a_qrefs_0p875_7:
  260. vdd_a_qrefs_0p875_8:
  261. vdd_a_qrefs_0p875_9:
  262. vdd_a_ufs_0_core:
  263. vdd_a_usbhs_core:
  264. vreg_l10c_0p88: ldo10 {
  265. regulator-min-microvolt = <720000>;
  266. regulator-max-microvolt = <1050000>;
  267. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  268. };
  269. vreg_l11c_2p8: ldo11 {
  270. regulator-min-microvolt = <2800000>;
  271. regulator-max-microvolt = <3544000>;
  272. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  273. };
  274. vreg_l12c_1p8: ldo12 {
  275. regulator-min-microvolt = <1650000>;
  276. regulator-max-microvolt = <2000000>;
  277. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  278. };
  279. vreg_l13c_3p0: ldo13 {
  280. regulator-min-microvolt = <2700000>;
  281. regulator-max-microvolt = <3544000>;
  282. regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
  283. };
  284. vdd_flash:
  285. vdd_iris_rgb:
  286. vdd_mic_bias:
  287. vreg_bob: bob {
  288. regulator-min-microvolt = <3008000>;
  289. regulator-max-microvolt = <3960000>;
  290. regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
  291. };
  292. };
  293. };
  294. /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
  295. &ipa {
  296. status = "okay";
  297. modem-init;
  298. };
  299. &lpass_va_macro {
  300. vdd-micb-supply = <&vreg_bob>;
  301. };
  302. /* NOTE: Not all Qcards have eDP connector stuffed */
  303. &mdss_edp {
  304. aux-bus {
  305. edp_panel: panel {
  306. compatible = "edp-panel";
  307. backlight = <&pm8350c_pwm_backlight>;
  308. ports {
  309. #address-cells = <1>;
  310. #size-cells = <0>;
  311. port@0 {
  312. reg = <0>;
  313. edp_panel_in: endpoint {
  314. remote-endpoint = <&mdss_edp_out>;
  315. };
  316. };
  317. };
  318. };
  319. };
  320. };
  321. &mdss_edp_out {
  322. remote-endpoint = <&edp_panel_in>;
  323. };
  324. &mdss_edp_phy {
  325. vdda-pll-supply = <&vdd_a_edp_0_0p9>;
  326. vdda-phy-supply = <&vdd_a_edp_0_1p2>;
  327. };
  328. &pcie1_phy {
  329. vdda-phy-supply = <&vreg_l10c_0p88>;
  330. vdda-pll-supply = <&vreg_l6b_1p2>;
  331. };
  332. &pm8350c_pwm {
  333. pinctrl-names = "default";
  334. pinctrl-0 = <&pmic_edp_bl_pwm>;
  335. };
  336. &pmk8350_vadc {
  337. pmk8350-die-temp@3 {
  338. reg = <PMK8350_ADC7_DIE_TEMP>;
  339. label = "pmk8350_die_temp";
  340. qcom,pre-scaling = <1 1>;
  341. };
  342. pmr735a-die-temp@403 {
  343. reg = <PMR735A_ADC7_DIE_TEMP>;
  344. label = "pmr735a_die_temp";
  345. qcom,pre-scaling = <1 1>;
  346. };
  347. };
  348. &qfprom {
  349. vcc-supply = <&vdd_qfprom>;
  350. };
  351. /* For eMMC. NOTE: not all Qcards have eMMC stuffed */
  352. &sdhc_1 {
  353. vmmc-supply = <&vreg_l7b_2p5>;
  354. vqmmc-supply = <&vreg_l19b_1p8>;
  355. non-removable;
  356. no-sd;
  357. no-sdio;
  358. };
  359. &swr0 {
  360. wcd_rx: codec@0,4 {
  361. compatible = "sdw20217010d00";
  362. reg = <0 4>;
  363. qcom,rx-port-mapping = <1 2 3 4 5>;
  364. };
  365. };
  366. &swr1 {
  367. wcd_tx: codec@0,3 {
  368. compatible = "sdw20217010d00";
  369. reg = <0 3>;
  370. qcom,tx-port-mapping = <1 2 3 4>;
  371. };
  372. };
  373. uart_dbg: &uart5 {
  374. compatible = "qcom,geni-debug-uart";
  375. status = "okay";
  376. };
  377. mos_bt_uart: &uart7 {
  378. status = "okay";
  379. /delete-property/ interrupts;
  380. interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
  381. <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
  382. pinctrl-names = "default", "sleep";
  383. pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
  384. bluetooth: bluetooth {
  385. compatible = "qcom,wcn6750-bt";
  386. pinctrl-names = "default";
  387. pinctrl-0 = <&mos_bt_en>;
  388. enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
  389. swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
  390. vddaon-supply = <&vreg_s7b_0p952>;
  391. vddbtcxmx-supply = <&vreg_s7b_0p952>;
  392. vddrfacmn-supply = <&vreg_s7b_0p952>;
  393. vddrfa0p8-supply = <&vreg_s7b_0p952>;
  394. vddrfa1p7-supply = <&vdd19_pmu_rfa_i>;
  395. vddrfa1p2-supply = <&vdd13_pmu_rfa_i>;
  396. vddrfa2p2-supply = <&vreg_s1c_2p2>;
  397. vddasd-supply = <&vreg_l11c_2p8>;
  398. vddio-supply = <&vreg_l18b_1p8>;
  399. max-speed = <3200000>;
  400. };
  401. };
  402. &usb_1_hsphy {
  403. vdda-pll-supply = <&vdd_a_usbhs_core>;
  404. vdda33-supply = <&vdd_a_usbhs_3p1>;
  405. vdda18-supply = <&vdd_a_usbhs_1p8>;
  406. };
  407. &usb_1_qmpphy {
  408. vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>;
  409. vdda-pll-supply = <&vdd_a_usbssdp_0_core>;
  410. };
  411. &usb_2_hsphy {
  412. vdda-pll-supply = <&vdd_a_usbhs_core>;
  413. vdda33-supply = <&vdd_a_usbhs_3p1>;
  414. vdda18-supply = <&vdd_a_usbhs_1p8>;
  415. };
  416. /*
  417. * PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES
  418. *
  419. * NOTE: In general if pins leave the Qcard then the pinctrl goes in the
  420. * baseboard or board device tree, not here.
  421. */
  422. /* No external pull for eDP HPD, so set the internal one. */
  423. &edp_hot_plug_det {
  424. bias-pull-down;
  425. };
  426. /*
  427. * For ts_i2c
  428. *
  429. * Technically this i2c bus actually leaves the Qcard, but it leaves directly
  430. * via the eDP connector (it doesn't hit the baseboard). The external pulls
  431. * are on Qcard.
  432. */
  433. &qup_i2c13_data_clk {
  434. /* Has external pull */
  435. bias-disable;
  436. drive-strength = <2>;
  437. };
  438. /* For mos_bt_uart */
  439. &qup_uart7_cts {
  440. /*
  441. * Configure a bias-bus-hold on CTS to lower power
  442. * usage when Bluetooth is turned off. Bus hold will
  443. * maintain a low power state regardless of whether
  444. * the Bluetooth module drives the pin in either
  445. * direction or leaves the pin fully unpowered.
  446. */
  447. bias-bus-hold;
  448. };
  449. /* For mos_bt_uart */
  450. &qup_uart7_rts {
  451. /* We'll drive RTS, so no pull */
  452. bias-disable;
  453. drive-strength = <2>;
  454. };
  455. /* For mos_bt_uart */
  456. &qup_uart7_tx {
  457. /* We'll drive TX, so no pull */
  458. bias-disable;
  459. drive-strength = <2>;
  460. };
  461. /* For mos_bt_uart */
  462. &qup_uart7_rx {
  463. /*
  464. * Configure a pull-up on RX. This is needed to avoid
  465. * garbage data when the TX pin of the Bluetooth module is
  466. * in tri-state (module powered off or not driving the
  467. * signal yet).
  468. */
  469. bias-pull-up;
  470. };
  471. /* eMMC, if stuffed, is straight on the Qcard */
  472. &sdc1_clk {
  473. bias-disable;
  474. drive-strength = <16>;
  475. };
  476. &sdc1_cmd {
  477. bias-pull-up;
  478. drive-strength = <10>;
  479. };
  480. &sdc1_data {
  481. bias-pull-up;
  482. drive-strength = <10>;
  483. };
  484. &sdc1_rclk {
  485. bias-pull-down;
  486. };
  487. /*
  488. * PINCTRL - QCARD
  489. *
  490. * This has entries that are defined by Qcard even if they go to the main
  491. * board. In cases where the pulls may be board dependent we defer those
  492. * settings to the board device tree. Drive strengths tend to be assinged here
  493. * but could conceivably be overwridden by board device trees.
  494. */
  495. &pm8350c_gpios {
  496. pmic_edp_bl_en: pmic-edp-bl-en-state {
  497. pins = "gpio7";
  498. function = "normal";
  499. bias-disable;
  500. qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
  501. /* Force backlight to be disabled to match state at boot. */
  502. output-low;
  503. };
  504. pmic_edp_bl_pwm: pmic-edp-bl-pwm-state {
  505. pins = "gpio8";
  506. function = "func1";
  507. bias-disable;
  508. qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
  509. output-low;
  510. power-source = <0>;
  511. };
  512. };
  513. &tlmm {
  514. mos_bt_en: mos-bt-en-pins {
  515. pins = "gpio85";
  516. function = "gpio";
  517. drive-strength = <2>;
  518. output-low;
  519. };
  520. /* For mos_bt_uart */
  521. qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins {
  522. pins = "gpio28";
  523. function = "gpio";
  524. /*
  525. * Configure a bias-bus-hold on CTS to lower power
  526. * usage when Bluetooth is turned off. Bus hold will
  527. * maintain a low power state regardless of whether
  528. * the Bluetooth module drives the pin in either
  529. * direction or leaves the pin fully unpowered.
  530. */
  531. bias-bus-hold;
  532. };
  533. /* For mos_bt_uart */
  534. qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins {
  535. pins = "gpio29";
  536. function = "gpio";
  537. /*
  538. * Configure pull-down on RTS. As RTS is active low
  539. * signal, pull it low to indicate the BT SoC that it
  540. * can wakeup the system anytime from suspend state by
  541. * pulling RX low (by sending wakeup bytes).
  542. */
  543. bias-pull-down;
  544. };
  545. /* For mos_bt_uart */
  546. qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins {
  547. pins = "gpio31";
  548. function = "gpio";
  549. /*
  550. * Configure a pull-up on RX. This is needed to avoid
  551. * garbage data when the TX pin of the Bluetooth module
  552. * is floating which may cause spurious wakeups.
  553. */
  554. bias-pull-up;
  555. };
  556. /* For mos_bt_uart */
  557. qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins {
  558. pins = "gpio30";
  559. function = "gpio";
  560. /*
  561. * Configure pull-up on TX when it isn't actively driven
  562. * to prevent BT SoC from receiving garbage during sleep.
  563. */
  564. bias-pull-up;
  565. };
  566. ts_int_conn: ts-int-conn-pins {
  567. pins = "gpio55";
  568. function = "gpio";
  569. bias-pull-up;
  570. };
  571. ts_rst_conn: ts-rst-conn-pins {
  572. pins = "gpio54";
  573. function = "gpio";
  574. drive-strength = <2>;
  575. };
  576. us_euro_hs_sel: us-euro-hs-sel {
  577. pins = "gpio81";
  578. function = "gpio";
  579. bias-pull-down;
  580. drive-strength = <2>;
  581. };
  582. wcd_reset_n: wcd-reset-n {
  583. pins = "gpio83";
  584. function = "gpio";
  585. drive-strength = <8>;
  586. };
  587. wcd_reset_n_sleep: wcd-reset-n-sleep {
  588. pins = "gpio83";
  589. function = "gpio";
  590. drive-strength = <8>;
  591. bias-disable;
  592. };
  593. };