sc7280-herobrine-crd.dts 6.8 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * sc7280 CRD 3+ board device tree source
  4. *
  5. * Copyright 2022 Google LLC.
  6. */
  7. /dts-v1/;
  8. #include "sc7280-herobrine.dtsi"
  9. #include "sc7280-herobrine-audio-wcd9385.dtsi"
  10. #include "sc7280-herobrine-lte-sku.dtsi"
  11. / {
  12. model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
  13. compatible = "google,zoglin", "google,hoglin", "qcom,sc7280";
  14. /* FIXED REGULATORS */
  15. /*
  16. * On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL.
  17. * However, on CRD there's an extra regulator in the way. Since this
  18. * is expected to be uncommon, we'll leave the "vreg_edp_bl" label
  19. * in the baseboard herobrine.dtsi point at "ppvar_sys" and then
  20. * make a "_crd" specific version here.
  21. */
  22. vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
  23. compatible = "regulator-fixed";
  24. regulator-name = "vreg_edp_bl_crd";
  25. gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>;
  26. enable-active-high;
  27. pinctrl-names = "default";
  28. pinctrl-0 = <&edp_bl_reg_en>;
  29. vin-supply = <&ppvar_sys>;
  30. };
  31. };
  32. /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
  33. &apps_rsc {
  34. pmg1110-regulators {
  35. compatible = "qcom,pmg1110-rpmh-regulators";
  36. qcom,pmic-id = "k";
  37. vreg_s1k_1p0: smps1 {
  38. regulator-min-microvolt = <1010000>;
  39. regulator-max-microvolt = <1170000>;
  40. };
  41. };
  42. };
  43. ap_tp_i2c: &i2c0 {
  44. status = "okay";
  45. clock-frequency = <400000>;
  46. trackpad: trackpad@15 {
  47. compatible = "hid-over-i2c";
  48. reg = <0x15>;
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&tp_int_odl>;
  51. interrupt-parent = <&tlmm>;
  52. interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
  53. post-power-on-delay-ms = <20>;
  54. hid-descr-addr = <0x0001>;
  55. vdd-supply = <&pp3300_z1>;
  56. wakeup-source;
  57. };
  58. };
  59. &ap_sar_sensor_i2c {
  60. status = "okay";
  61. };
  62. &ap_sar_sensor0 {
  63. status = "okay";
  64. };
  65. &ap_sar_sensor1 {
  66. status = "okay";
  67. };
  68. ap_ts_pen_1v8: &i2c13 {
  69. status = "okay";
  70. clock-frequency = <400000>;
  71. ap_ts: touchscreen@5c {
  72. compatible = "hid-over-i2c";
  73. reg = <0x5c>;
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
  76. interrupt-parent = <&tlmm>;
  77. interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
  78. post-power-on-delay-ms = <500>;
  79. hid-descr-addr = <0x0000>;
  80. vdd-supply = <&pp3300_left_in_mlb>;
  81. };
  82. };
  83. &mdss_edp {
  84. status = "okay";
  85. };
  86. &mdss_edp_phy {
  87. status = "okay";
  88. };
  89. /* For nvme */
  90. &pcie1 {
  91. status = "okay";
  92. };
  93. /* For nvme */
  94. &pcie1_phy {
  95. status = "okay";
  96. };
  97. &pm8350c_pwm_backlight {
  98. power-supply = <&vreg_edp_bl_crd>;
  99. };
  100. /* For eMMC */
  101. &sdhc_1 {
  102. status = "okay";
  103. };
  104. /* For SD Card */
  105. &sdhc_2 {
  106. status = "okay";
  107. };
  108. /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
  109. /*
  110. * This pin goes to the display panel but then doesn't actually do anything
  111. * on the panel itself (it doesn't connect to the touchscreen controller).
  112. * We'll set a pullup here just to park the line.
  113. */
  114. &ts_rst_conn {
  115. bias-pull-up;
  116. };
  117. /* PINCTRL - BOARD-SPECIFIC */
  118. /*
  119. * Methodology for gpio-line-names:
  120. * - If a pin goes to CRD board and is named it gets that name.
  121. * - If a pin goes to CRD board and is not named, it gets no name.
  122. * - If a pin is totally internal to Qcard then it gets Qcard name.
  123. * - If a pin is not hooked up on Qcard, it gets no name.
  124. */
  125. &pm8350c_gpios {
  126. gpio-line-names = "FLASH_STROBE_1", /* 1 */
  127. "AP_SUSPEND",
  128. "PM8008_1_RST_N",
  129. "",
  130. "",
  131. "EDP_BL_REG_EN",
  132. "PMIC_EDP_BL_EN",
  133. "PMIC_EDP_BL_PWM",
  134. "";
  135. edp_bl_reg_en: edp-bl-reg-en-state {
  136. pins = "gpio6";
  137. function = "normal";
  138. bias-disable;
  139. qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
  140. };
  141. };
  142. &tlmm {
  143. gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
  144. "AP_TP_I2C_SCL",
  145. "PCIE1_RESET_N",
  146. "PCIE1_WAKE_N",
  147. "APPS_I2C_SDA",
  148. "APPS_I2C_SCL",
  149. "",
  150. "TPAD_INT_N",
  151. "",
  152. "",
  153. "GNSS_L1_EN", /* 10 */
  154. "GNSS_L5_EN",
  155. "QSPI_DATA_0",
  156. "QSPI_DATA_1",
  157. "QSPI_CLK",
  158. "QSPI_CS_N_1",
  159. /*
  160. * AP_FLASH_WP is crossystem ABI. Schematics call it
  161. * BIOS_FLASH_WP_L (the '_L' suffix is misleading, the
  162. * signal is active high).
  163. */
  164. "AP_FLASH_WP",
  165. "",
  166. "AP_EC_INT_N",
  167. "",
  168. "CAM0_RST_N", /* 20 */
  169. "CAM1_RST_N",
  170. "SM_DBG_UART_TX",
  171. "SM_DBG_UART_RX",
  172. "",
  173. "PM8008_IRQ_1",
  174. "HOST2WLAN_SOL",
  175. "WLAN2HOST_SOL",
  176. "MOS_BT_UART_CTS",
  177. "MOS_BT_UART_RFR",
  178. "MOS_BT_UART_TX", /* 30 */
  179. "MOS_BT_UART_RX",
  180. "",
  181. "HUB_RST",
  182. "",
  183. "",
  184. "",
  185. "",
  186. "",
  187. "",
  188. "EC_SPI_MISO_GPIO40", /* 40 */
  189. "EC_SPI_MOSI_GPIO41",
  190. "EC_SPI_CLK_GPIO42",
  191. "EC_SPI_CS_GPIO43",
  192. "",
  193. "EARLY_EUD_EN",
  194. "",
  195. "DP_HOT_PLUG_DETECT",
  196. "AP_BRD_ID_0",
  197. "AP_BRD_ID_1",
  198. "AP_BRD_ID_2", /* 50 */
  199. "NVME_PWR_REG_EN",
  200. "TS_I2C_SDA_CONN",
  201. "TS_I2C_CLK_CONN",
  202. "TS_RST_CONN",
  203. "TS_INT_CONN",
  204. "AP_I2C_TPM_SDA",
  205. "AP_I2C_TPM_SCL",
  206. "",
  207. "",
  208. "EDP_HOT_PLUG_DET_N", /* 60 */
  209. "",
  210. "",
  211. "AMP_EN",
  212. "CAM0_MCLK_GPIO_64",
  213. "CAM1_MCLK_GPIO_65",
  214. "",
  215. "",
  216. "",
  217. "CCI_I2C_SDA0",
  218. "CCI_I2C_SCL0", /* 70 */
  219. "",
  220. "",
  221. "",
  222. "",
  223. "",
  224. "",
  225. "",
  226. "",
  227. "PCIE1_CLK_REQ_N",
  228. "EN_PP3300_DX_EDP", /* 80 */
  229. "US_EURO_HS_SEL",
  230. "FORCED_USB_BOOT",
  231. "WCD_RESET_N",
  232. "MOS_WLAN_EN",
  233. "MOS_BT_EN",
  234. "MOS_SW_CTRL",
  235. "MOS_PCIE0_RST",
  236. "MOS_PCIE0_CLKREQ_N",
  237. "MOS_PCIE0_WAKE_N",
  238. "MOS_LAA_AS_EN", /* 90 */
  239. "SD_CARD_DET_CONN",
  240. "",
  241. "",
  242. "MOS_BT_WLAN_SLIMBUS_CLK",
  243. "MOS_BT_WLAN_SLIMBUS_DAT0",
  244. "",
  245. "",
  246. "",
  247. "",
  248. "", /* 100 */
  249. "",
  250. "",
  251. "",
  252. "H1_AP_INT_N",
  253. "",
  254. "AMP_BCLK",
  255. "AMP_DIN",
  256. "AMP_LRCLK",
  257. "UIM1_DATA_GPIO_109",
  258. "UIM1_CLK_GPIO_110", /* 110 */
  259. "UIM1_RESET_GPIO_111",
  260. "",
  261. "UIM1_DATA",
  262. "UIM1_CLK",
  263. "UIM1_RESET",
  264. "UIM1_PRESENT",
  265. "SDM_RFFE0_CLK",
  266. "SDM_RFFE0_DATA",
  267. "",
  268. "SDM_RFFE1_DATA", /* 120 */
  269. "SC_GPIO_121",
  270. "FASTBOOT_SEL_1",
  271. "SC_GPIO_123",
  272. "FASTBOOT_SEL_2",
  273. "SM_RFFE4_CLK_GRFC_8",
  274. "SM_RFFE4_DATA_GRFC_9",
  275. "WLAN_COEX_UART1_RX",
  276. "WLAN_COEX_UART1_TX",
  277. "",
  278. "", /* 130 */
  279. "",
  280. "",
  281. "SDR_QLINK_REQ",
  282. "SDR_QLINK_EN",
  283. "QLINK0_WMSS_RESET_N",
  284. "SMR526_QLINK1_REQ",
  285. "SMR526_QLINK1_EN",
  286. "SMR526_QLINK1_WMSS_RESET_N",
  287. "",
  288. "SAR1_INT_N", /* 140 */
  289. "SAR0_INT_N",
  290. "",
  291. "",
  292. "WCD_SWR_TX_CLK",
  293. "WCD_SWR_TX_DATA0",
  294. "WCD_SWR_TX_DATA1",
  295. "WCD_SWR_RX_CLK",
  296. "WCD_SWR_RX_DATA0",
  297. "WCD_SWR_RX_DATA1",
  298. "DMIC01_CLK", /* 150 */
  299. "DMIC01_DATA",
  300. "DMIC23_CLK",
  301. "DMIC23_DATA",
  302. "",
  303. "",
  304. "EC_IN_RW_N",
  305. "EN_PP3300_HUB",
  306. "WCD_SWR_TX_DATA2",
  307. "",
  308. "", /* 160 */
  309. "",
  310. "",
  311. "",
  312. "",
  313. "",
  314. "",
  315. "",
  316. "",
  317. "",
  318. "", /* 170 */
  319. "MOS_BLE_UART_TX",
  320. "MOS_BLE_UART_RX",
  321. "";
  322. };